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| author | Bin Meng <bin.meng@windriver.com> | 2021-01-23 18:39:54 +0800 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-01-24 18:53:20 +0100 |
| commit | 281c5c95b259a0d9809977c9f407d4654c3a79aa (patch) | |
| tree | d80ad0f068e2dcac1acf73d6f9c6632ddd3ec034 /hw/scsi/esp-pci.c | |
| parent | e93c65a6c64fa18b0c61fb9338d364cbea32b6ef (diff) | |
hw/sd: ssi-sd: Fix incorrect card response sequence
Per the "Physical Layer Specification Version 8.00" chapter 7.5.1,
"Command/Response", there is a minimum 8 clock cycles (Ncr) before
the card response shows up on the data out line. However current
implementation jumps directly to the sending response state after
all 6 bytes command is received, which is a spec violation.
Add a new state PREP_RESP in the ssi-sd state machine to handle it.
Fixes: 775616c3ae8c ("Partial SD card SPI mode support")
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210123104016.17485-4-bmeng.cn@gmail.com>
[PMD: Change VMState version id 2 -> 3]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'hw/scsi/esp-pci.c')
0 files changed, 0 insertions, 0 deletions