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authorMichael Clark <mjc@sifive.com>2018-03-06 10:51:53 +1300
committerPalmer Dabbelt <palmer@sifive.com>2018-10-17 13:02:19 -0700
commit426f03482c8d2b98613f92a76bd034ac6bb0bc7a (patch)
tree9b895f90a191e0abd95795dcc26cd0578f41fb2d /hw/riscv
parentdf354dd41064491342c2f1b5d4743eed40f0fa27 (diff)
RISC-V: Update CSR and interrupt definitions
* Add user-mode CSR defininitions. * Reorder CSR definitions to match the specification. * Change H mode interrupt comment to 'reserved'. * Remove unused X_COP interrupt. * Add user-mode interrupts. * Remove erroneous until comments on machine mode interrupts. * Move together paging mode and page table bit definitions. * Move together interrupt and exception cause definitions. Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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