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authorAlistair Francis <alistair.francis@wdc.com>2021-10-25 14:06:57 +1000
committerAlistair Francis <alistair.francis@wdc.com>2021-10-28 14:39:23 +1000
commit9b144ed444f1fb3149d9ec17f0c4a64d4fd7d662 (patch)
treebebad93a529e980b70d00ad2e48bc895a1d5ed82 /hw/riscv
parent7d10ff8a4de7a9bff1e7b25011f5eb43f24a6713 (diff)
hw/riscv: opentitan: Fixup the PLIC context addresses
Fixup the PLIC context address to correctly support the threshold and claim register. Fixes: ef63100648 ("hw/riscv: opentitan: Update to the latest build") Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20211025040657.262696-1-alistair.francis@opensource.wdc.com
Diffstat (limited to 'hw/riscv')
-rw-r--r--hw/riscv/opentitan.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 83e1511f28..c531450b9f 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -161,8 +161,8 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000);
qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000);
qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 0x18);
- qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200004);
- qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 4);
+ qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200000);
+ qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 8);
qdev_prop_set_uint32(DEVICE(&s->plic), "aperture-size", memmap[IBEX_DEV_PLIC].size);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) {