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authorBin Meng <bmeng.cn@gmail.com>2021-07-08 22:33:19 +0800
committerAlistair Francis <alistair.francis@wdc.com>2021-07-15 08:56:00 +1000
commit623d53cb017fc1506eed71dd01792bef1062a877 (patch)
tree64a4a6c4f21c88ff6f40cc627465e719e48b83e4 /hw/riscv
parent074ca702e64dcea15c9c3b2c1931351cf397debe (diff)
hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned
Currently the firmware dynamic info (fw_dyn) is put right after the reset vector, which is not 8-byte aligned on RV64. OpenSBI fw_dynamic uses ld to read contents from 'struct fw_dynamic_info', which expects fw_dyn to be on the 8-byte boundary, otherwise the misaligned load exception may happen. Fortunately this does not cause any issue on QEMU, as QEMU does support misaligned load. RV32 does not have any issue as it is 4-byte aligned already. Change to make sure it is 8-byte aligned which works for both RV32 and RV64. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210708143319.10441-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv')
-rw-r--r--hw/riscv/sifive_u.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index e75ca38783..87bbd10b21 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -602,10 +602,10 @@ static void sifive_u_machine_init(MachineState *machine)
}
/* reset vector */
- uint32_t reset_vec[11] = {
+ uint32_t reset_vec[12] = {
s->msel, /* MSEL pin state */
0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */
- 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */
+ 0x02c28613, /* addi a2, t0, %pcrel_lo(1b) */
0xf1402573, /* csrr a0, mhartid */
0,
0,
@@ -614,6 +614,7 @@ static void sifive_u_machine_init(MachineState *machine)
start_addr_hi32,
fdt_load_addr, /* fdt_laddr: .dword */
0x00000000,
+ 0x00000000,
/* fw_dyn: */
};
if (riscv_is_32bit(&s->soc.u_cpus)) {