diff options
| author | Bin Meng <bmeng.cn@gmail.com> | 2019-09-06 09:19:54 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-09-17 08:42:45 -0700 |
| commit | a2360c854fb56f9506d81be8b86ba577c0dbefc3 (patch) | |
| tree | d9d144cc02f62ab49e18c5a570d2025c81ba3786 /hw/riscv | |
| parent | 9f79638ec55411d5d120a15bd2181cc862e4fba1 (diff) | |
riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead
Replace the call to hw_error() with qemu_log_mask(LOG_GUEST_ERROR,...)
in various sifive models.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'hw/riscv')
| -rw-r--r-- | hw/riscv/sifive_prci.c | 8 | ||||
| -rw-r--r-- | hw/riscv/sifive_test.c | 5 | ||||
| -rw-r--r-- | hw/riscv/sifive_uart.c | 9 |
3 files changed, 13 insertions, 9 deletions
diff --git a/hw/riscv/sifive_prci.c b/hw/riscv/sifive_prci.c index 562bc3dc4c..982fbb26fd 100644 --- a/hw/riscv/sifive_prci.c +++ b/hw/riscv/sifive_prci.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "hw/sysbus.h" +#include "qemu/log.h" #include "qemu/module.h" #include "target/riscv/cpu.h" #include "hw/hw.h" @@ -38,7 +39,8 @@ static uint64_t sifive_prci_read(void *opaque, hwaddr addr, unsigned int size) case SIFIVE_PRCI_PLLOUTDIV: return s->plloutdiv; } - hw_error("%s: read: addr=0x%x\n", __func__, (int)addr); + qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%x\n", + __func__, (int)addr); return 0; } @@ -66,8 +68,8 @@ static void sifive_prci_write(void *opaque, hwaddr addr, s->plloutdiv = (uint32_t) val64; break; default: - hw_error("%s: bad write: addr=0x%x v=0x%x\n", - __func__, (int)addr, (int)val64); + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%x v=0x%x\n", + __func__, (int)addr, (int)val64); } } diff --git a/hw/riscv/sifive_test.c b/hw/riscv/sifive_test.c index 711740939e..aa544e7428 100644 --- a/hw/riscv/sifive_test.c +++ b/hw/riscv/sifive_test.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "hw/sysbus.h" +#include "qemu/log.h" #include "qemu/module.h" #include "sysemu/runstate.h" #include "target/riscv/cpu.h" @@ -49,8 +50,8 @@ static void sifive_test_write(void *opaque, hwaddr addr, break; } } - hw_error("%s: write: addr=0x%x val=0x%016" PRIx64 "\n", - __func__, (int)addr, val64); + qemu_log_mask(LOG_GUEST_ERROR, "%s: write: addr=0x%x val=0x%016" PRIx64 "\n", + __func__, (int)addr, val64); } static const MemoryRegionOps sifive_test_ops = { diff --git a/hw/riscv/sifive_uart.c b/hw/riscv/sifive_uart.c index 9de42b1680..215990b443 100644 --- a/hw/riscv/sifive_uart.c +++ b/hw/riscv/sifive_uart.c @@ -18,6 +18,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" +#include "qemu/log.h" #include "hw/sysbus.h" #include "chardev/char.h" #include "chardev/char-fe.h" @@ -95,8 +96,8 @@ uart_read(void *opaque, hwaddr addr, unsigned int size) return s->div; } - hw_error("%s: bad read: addr=0x%x\n", - __func__, (int)addr); + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read: addr=0x%x\n", + __func__, (int)addr); return 0; } @@ -127,8 +128,8 @@ uart_write(void *opaque, hwaddr addr, s->div = val64; return; } - hw_error("%s: bad write: addr=0x%x v=0x%x\n", - __func__, (int)addr, (int)value); + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%x v=0x%x\n", + __func__, (int)addr, (int)value); } static const MemoryRegionOps uart_ops = { |