diff options
| author | Fabien Chouteau <chouteau@adacore.com> | 2019-02-12 18:38:39 +0100 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-05-24 11:58:30 -0700 |
| commit | 30efbf330a45fc5b83457037927151adafc397ed (patch) | |
| tree | 89111532c51d904f467ed1d879c239a775d5a43c /hw/riscv/trace-events | |
| parent | a7b21f6762a2d6ec08106d8a7ccb11829914523f (diff) | |
SiFive RISC-V GPIO Device
QEMU model of the GPIO device on the SiFive E300 series SOCs.
The pins are not used by a board definition yet, however this
implementation can already be used to trigger GPIO interrupts from the
software by configuring a pin as both output and input.
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'hw/riscv/trace-events')
| -rw-r--r-- | hw/riscv/trace-events | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/hw/riscv/trace-events b/hw/riscv/trace-events new file mode 100644 index 0000000000..6d59233e23 --- /dev/null +++ b/hw/riscv/trace-events @@ -0,0 +1,7 @@ +# See docs/devel/tracing.txt for syntax documentation. + +# hw/gpio/sifive_gpio.c +sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64 +sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64 +sifive_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64 +sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64 |