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authorAnup Patel <anup.patel@wdc.com>2020-05-14 15:51:31 +0530
committerAlistair Francis <alistair.francis@wdc.com>2020-08-25 09:11:35 -0700
commit3bf03f08999b9a469a61279a04041bcbfadad6a8 (patch)
treee43634385ee0e9b1e634c22388d529857daa75d1 /hw/riscv/spike.c
parent7774e403f2ac58b3e87bfe8d2f77676501ba893e (diff)
hw/riscv: Allow creating multiple instances of CLINT
We extend CLINT emulation to allow multiple instances of CLINT in a QEMU RISC-V machine. To achieve this, we remove first HART id zero assumption from CLINT emulation. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Message-Id: <20200616032229.766089-2-anup.patel@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv/spike.c')
-rw-r--r--hw/riscv/spike.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 13958bdbeb..5d422b4944 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -234,7 +234,7 @@ static void spike_board_init(MachineState *machine)
/* Core Local Interruptor (timer and IPI) */
sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
- smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
+ 0, smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
false);
}