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authorMichael Clark <mjc@sifive.com>2018-03-03 14:30:07 +1300
committerMichael Clark <mjc@sifive.com>2018-05-06 10:39:38 +1200
commit2a8756ed7d64f8fed6ad50fb062f7118e47c856c (patch)
treee51ad53bef7471fad7c2ae36bc48ccf483a56238 /hw/riscv/spike.c
parentc8b7e627b4269a3bc3ae41d9f420547a47e6d9b9 (diff)
RISC-V: Replace hardcoded constants with enum values
The RISC-V device-tree code has a number of hard-coded constants and this change moves them into header enums. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv/spike.c')
-rw-r--r--hw/riscv/spike.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 62857e4fa0..ae82f4eb63 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -115,7 +115,8 @@ static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
g_free(nodename);
qemu_fdt_add_subnode(fdt, "/cpus");
- qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 10000000);
+ qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
+ SIFIVE_CLINT_TIMEBASE_FREQ);
qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
@@ -124,7 +125,8 @@ static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
char *isa = riscv_isa_string(&s->soc.harts[cpu]);
qemu_fdt_add_subnode(fdt, nodename);
- qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 1000000000);
+ qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
+ SPIKE_CLOCK_FREQ);
qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");