diff options
| author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-05-14 15:29:41 +0900 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-05-24 10:38:50 +1000 |
| commit | 91a3387dc42b261e95eb402bf7d043b3a043209c (patch) | |
| tree | 0ff25640b43fad1670ff5b932bdb2a8b59de8e96 /hw/riscv/sifive_u.c | |
| parent | 4bcfc391ac627155448951b45a8432eab91c2db9 (diff) | |
hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)
If specified CPU configuration is not valid, not just it prints error
message, it aborts and generates core dumps (depends on the operating
system). This kind of error handling should be used only when a serious
runtime error occurs.
This commit makes error handling on CPU configuration more generous on
sifive_e/u and opentitan machines. It now just prints error message and
quits (without coredumps and aborts).
This is separate from spike/virt because it involves different type
(TYPE_RISCV_HART_ARRAY) on sifive_e/u and opentitan machines.
Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <09e61e58a7543da44bdb0e0f5368afc8903b4aa6.1652509778.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv/sifive_u.c')
| -rw-r--r-- | hw/riscv/sifive_u.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index cc8c7637cb..a2495b5ae7 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -830,8 +830,8 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp) qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type); qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004); - sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort); - sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort); + sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_fatal); + sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_fatal); /* * The cluster must be realized after the RISC-V hart array container, * as the container's CPU object is only created on realize, and the |