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| author | Peter Maydell <peter.maydell@linaro.org> | 2019-01-03 10:42:21 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-01-03 10:42:21 +0000 |
| commit | 1b3e80082bcd9b760113bbc023496cd22efad2dc (patch) | |
| tree | 7922dee84ebb2b0104a470408c649032392d5ace /hw/riscv/sifive_u.c | |
| parent | 9b2e891ec5ccdb4a7d583b77988848282606fdea (diff) | |
| parent | 4250da10923347c9ee907f8d72bd93dfa5ee8742 (diff) | |
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20181226' into staging
Host support for riscv64.
Dead code elimination pass.
Register allocation improvements.
# gpg: Signature made Tue 25 Dec 2018 20:52:34 GMT
# gpg: using RSA key 64DF38E8AF7E215F
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>"
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* remotes/rth/tags/pull-tcg-20181226: (42 commits)
tcg: Improve call argument loading
tcg: Record register preferences during liveness
tcg: Add TCG_OPF_BB_EXIT
tcg: Split out more subroutines from liveness_pass_1
tcg: Rename and adjust liveness_pass_1 helpers
tcg: Reindent parts of liveness_pass_1
tcg: Dump register preference info with liveness
tcg: Improve register allocation for matching constraints
tcg: Add output_pref to TCGOp
tcg: Add preferred_reg argument to tcg_reg_alloc_do_movi
tcg: Add preferred_reg argument to temp_sync
tcg: Add preferred_reg argument to temp_load
tcg: Add preferred_reg argument to tcg_reg_alloc
tcg: Add reachable_code_pass
tcg: Reference count labels
tcg: Add TCG_CALL_NO_RETURN
tcg: Renumber TCG_CALL_* flags
linux-user: Add safe_syscall for riscv64 host
disas/microblaze: Remove unused REG_SP macro
configure: Add support for building RISC-V host
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/riscv/sifive_u.c')
0 files changed, 0 insertions, 0 deletions