diff options
author | Alistair Francis <alistair.francis@wdc.com> | 2020-05-13 10:37:08 -0700 |
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committer | Alistair Francis <alistair.francis@wdc.com> | 2020-06-03 09:11:51 -0700 |
commit | 0869490b1cc4d917ac4eb3a02cac7d71149def91 (patch) | |
tree | b0ee6cbea827562c00d57835ef1b34774e5ea9db /hw/riscv/sifive_e.c | |
parent | f33559a427134ff1ae49982bdca8d10f81837204 (diff) |
riscv: sifive_e: Manually define the machine
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'hw/riscv/sifive_e.c')
-rw-r--r-- | hw/riscv/sifive_e.c | 41 |
1 files changed, 30 insertions, 11 deletions
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index b53109521e..472a98970b 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -79,7 +79,7 @@ static void riscv_sifive_e_init(MachineState *machine) { const struct MemmapEntry *memmap = sifive_e_memmap; - SiFiveEState *s = g_new0(SiFiveEState, 1); + SiFiveEState *s = RISCV_E_MACHINE(machine); MemoryRegion *sys_mem = get_system_memory(); MemoryRegion *main_mem = g_new(MemoryRegion, 1); int i; @@ -115,6 +115,35 @@ static void riscv_sifive_e_init(MachineState *machine) } } +static void sifive_e_machine_instance_init(Object *obj) +{ +} + +static void sifive_e_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + + mc->desc = "RISC-V Board compatible with SiFive E SDK"; + mc->init = riscv_sifive_e_init; + mc->max_cpus = 1; + mc->default_cpu_type = SIFIVE_E_CPU; +} + +static const TypeInfo sifive_e_machine_typeinfo = { + .name = MACHINE_TYPE_NAME("sifive_e"), + .parent = TYPE_MACHINE, + .class_init = sifive_e_machine_class_init, + .instance_init = sifive_e_machine_instance_init, + .instance_size = sizeof(SiFiveEState), +}; + +static void sifive_e_machine_init_register_types(void) +{ + type_register_static(&sifive_e_machine_typeinfo); +} + +type_init(sifive_e_machine_init_register_types) + static void riscv_sifive_e_soc_init(Object *obj) { MachineState *ms = MACHINE(qdev_get_machine()); @@ -214,16 +243,6 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp) &s->xip_mem); } -static void riscv_sifive_e_machine_init(MachineClass *mc) -{ - mc->desc = "RISC-V Board compatible with SiFive E SDK"; - mc->init = riscv_sifive_e_init; - mc->max_cpus = 1; - mc->default_cpu_type = SIFIVE_E_CPU; -} - -DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init) - static void riscv_sifive_e_soc_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); |