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authorPeter Maydell <peter.maydell@linaro.org>2018-08-24 13:17:34 +0100
committerPeter Maydell <peter.maydell@linaro.org>2018-08-24 13:17:34 +0100
commitba3287d117066fef2ebfea9555197f94c950afc5 (patch)
treea4f2e4fa2a3b1dd1c70db649393608eecb74b4f4 /hw/riscv/sifive_clint.c
parentb558e295211deecdc769835a0a400f8aa59c53fd (diff)
hw/cpu/a15mpcore: If CPU has EL2, enable it on the GIC and wire it up
For the A15MPCore internal peripheral object, we handle GIC security extensions support by checking whether the CPUs have EL3 enabled; if so then we enable it also on the GIC. Handle the virtualization extensions in the same way: if the CPU has EL2 then enable it on the GIC and wire up the virtualization-specific memory regions and the maintenance interrupt. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Message-id: 20180821132811.17675-8-peter.maydell@linaro.org
Diffstat (limited to 'hw/riscv/sifive_clint.c')
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