diff options
| author | Bin Meng <bin.meng@windriver.com> | 2020-09-01 09:38:58 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-09-09 15:54:18 -0700 |
| commit | 73f6ed97acdbf7aec72d368fd5e16c00e04ac172 (patch) | |
| tree | b8e8f5ca6ba769ca3ac776411be5f2d75d72781b /hw/riscv/opentitan.c | |
| parent | 4100d5e6dc28cdd89d3eec6e4ddeb9d1a159c330 (diff) | |
target/riscv: cpu: Set reset vector based on the configured property value
Now that we have the newly introduced 'resetvec' property in the
RISC-V CPU and HART, instead of hard-coding the reset vector addr
in the CPU's instance_init(), move that to riscv_cpu_realize()
based on the configured property value from the RISC-V machines.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1598924352-89526-4-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv/opentitan.c')
| -rw-r--r-- | hw/riscv/opentitan.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 23ba3b4bfc..0531bd879b 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -111,6 +111,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) &error_abort); object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus, &error_abort); + object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8090, &error_abort); sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort); /* Boot ROM */ |