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| author | Bin Meng <bin.meng@windriver.com> | 2020-09-01 09:38:57 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-09-09 15:54:18 -0700 |
| commit | 4100d5e6dc28cdd89d3eec6e4ddeb9d1a159c330 (patch) | |
| tree | 8976db8de135bd8097e8902b4c261d3988893ee5 /hw/riscv/boot.c | |
| parent | 9b4c9b2b2a50fe4eb90d0ac2d8723b46ecb42511 (diff) | |
hw/riscv: hart: Add a new 'resetvec' property
RISC-V machines do not instantiate RISC-V CPUs directly, instead
they do that via the hart array. Add a new property for the reset
vector address to allow the value to be passed to the CPU, before
CPU is realized.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1598924352-89526-3-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv/boot.c')
0 files changed, 0 insertions, 0 deletions