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authorBin Meng <bmeng.cn@gmail.com>2019-09-06 09:20:08 -0700
committerPalmer Dabbelt <palmer@sifive.com>2019-09-17 08:42:47 -0700
commit0d95299468c8f19a306b93bb9b6940ea55945db5 (patch)
tree15b4eaa6206b97d9f17b37aba661496b73b7df9f /hw/riscv/Makefile.objs
parentef965ce23956a9e5cde5c9e91081484ec68a4139 (diff)
riscv: sifive: Implement PRCI model for FU540
This adds a simple PRCI model for FU540 (sifive_u). It has different register layout from the existing PRCI model for FE310 (sifive_e). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'hw/riscv/Makefile.objs')
-rw-r--r--hw/riscv/Makefile.objs1
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs
index c8596977a8..b95bbd51e2 100644
--- a/hw/riscv/Makefile.objs
+++ b/hw/riscv/Makefile.objs
@@ -8,6 +8,7 @@ obj-$(CONFIG_SIFIVE) += sifive_gpio.o
obj-$(CONFIG_SIFIVE) += sifive_plic.o
obj-$(CONFIG_SIFIVE) += sifive_test.o
obj-$(CONFIG_SIFIVE_U) += sifive_u.o
+obj-$(CONFIG_SIFIVE_U) += sifive_u_prci.o
obj-$(CONFIG_SIFIVE) += sifive_uart.o
obj-$(CONFIG_SPIKE) += spike.o
obj-$(CONFIG_RISCV_VIRT) += virt.o