diff options
author | balrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-11-17 14:07:13 +0000 |
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committer | balrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-11-17 14:07:13 +0000 |
commit | 38641a52f2335c470349c55d9b1679112da99399 (patch) | |
tree | bf249a04efe5bb74fd36c6cb99a8cdd3c95f3dbc /hw/pxa2xx.c | |
parent | 6c41b2723f5cac6e62e68925e7a73f30b11a7a06 (diff) |
Convert PXA2xx GPIOs and SCOOP GPIOs to a qemu_irq based api (similar to omap, max7310 and s3c gpios).
Convert spitz and gumstix boards to use new api.
Remove now obsolete gpio_handler_t definition.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3670 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/pxa2xx.c')
-rw-r--r-- | hw/pxa2xx.c | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/hw/pxa2xx.c b/hw/pxa2xx.c index 62c396cd33..9f7771f2d2 100644 --- a/hw/pxa2xx.c +++ b/hw/pxa2xx.c @@ -2013,9 +2013,10 @@ static struct pxa2xx_fir_s *pxa2xx_fir_init(target_phys_addr_t base, return s; } -void pxa2xx_reset(int line, int level, void *opaque) +static void pxa2xx_reset(void *opaque, int line, int level) { struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque; + if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */ cpu_reset(s->env); /* TODO: reset peripherals */ @@ -2046,6 +2047,8 @@ struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size, register_savevm("cpu", 0, ARM_CPU_SAVE_VERSION, cpu_save, cpu_load, s->env); + s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0]; + /* SDRAM & Internal Memory Storage */ cpu_register_physical_memory(PXA2XX_SDRAM_BASE, sdram_size, qemu_ram_alloc(sdram_size) | IO_MEM_RAM); @@ -2139,7 +2142,7 @@ struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size, /* GPIO1 resets the processor */ /* The handler can be overridden by board-specific code */ - pxa2xx_gpio_handler_set(s->gpio, 1, pxa2xx_reset, s); + pxa2xx_gpio_out_set(s->gpio, 1, s->reset); return s; } @@ -2161,6 +2164,8 @@ struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size, register_savevm("cpu", 0, ARM_CPU_SAVE_VERSION, cpu_save, cpu_load, s->env); + s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0]; + /* SDRAM & Internal Memory Storage */ cpu_register_physical_memory(PXA2XX_SDRAM_BASE, sdram_size, qemu_ram_alloc(sdram_size) | IO_MEM_RAM); @@ -2253,6 +2258,6 @@ struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size, /* GPIO1 resets the processor */ /* The handler can be overridden by board-specific code */ - pxa2xx_gpio_handler_set(s->gpio, 1, pxa2xx_reset, s); + pxa2xx_gpio_out_set(s->gpio, 1, s->reset); return s; } |