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authorNicholas Piggin <npiggin@gmail.com>2020-05-07 21:48:24 +1000
committerDavid Gibson <david@gibson.dropbear.id.au>2020-05-27 15:27:25 +1000
commitfe837714f3462e02e856d441ea6e9a6a0aad4695 (patch)
treeb6902c86008e69532373a45eeda7d66a941cf321 /hw/ppc
parentddc760832fa8cf5e93b9d9e6e854a5114ac63510 (diff)
ppc/pnv: Fix NMI system reset SRR1 value
Commit a77fed5bd926 ("ppc/pnv: Add support for NMI interface") got the SRR1 setting wrong for sresets that hit outside of power-save states. Fix this, better documenting the source for the bit definitions. Fixes: 01b552b05b0f ("ppc/pnv: Add support for NMI interface") Cc: Cédric Le Goater <clg@kaod.org> Cc: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-Id: <20200507114824.788942-1-npiggin@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> [dwg: Fixed up some tab indentation] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'hw/ppc')
-rw-r--r--hw/ppc/pnv.c26
1 files changed, 20 insertions, 6 deletions
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index da637822f9..f48a61d6d1 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1984,12 +1984,26 @@ static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
cpu_synchronize_state(cs);
ppc_cpu_do_system_reset(cs);
- /*
- * SRR1[42:45] is set to 0100 which the ISA defines as implementation
- * dependent. POWER processors use this for xscom triggered interrupts,
- * which come from the BMC or NMI IPIs.
- */
- env->spr[SPR_SRR1] |= PPC_BIT(43);
+ if (env->spr[SPR_SRR1] & PPC_BITMASK(46, 47)) {
+ /*
+ * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the
+ * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100
+ * (PPC_BIT(43)).
+ */
+ if (!(env->spr[SPR_SRR1] & PPC_BIT(43))) {
+ warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason");
+ env->spr[SPR_SRR1] |= PPC_BIT(43);
+ }
+ } else {
+ /*
+ * For non-powersave system resets, SRR1[42:45] are defined to be
+ * implementation-dependent. The POWER9 User Manual specifies that
+ * an external (SCOM driven, which may come from a BMC nmi command or
+ * another CPU requesting a NMI IPI) system reset exception should be
+ * 0b0010 (PPC_BIT(44)).
+ */
+ env->spr[SPR_SRR1] |= PPC_BIT(44);
+ }
}
static void pnv_nmi(NMIState *n, int cpu_index, Error **errp)