diff options
| author | Jan Kiszka <jan.kiszka@siemens.com> | 2009-05-02 00:29:37 +0200 |
|---|---|---|
| committer | Anthony Liguori <aliguori@us.ibm.com> | 2009-05-22 10:50:34 -0500 |
| commit | 8217606e6edb49591b4a6fd5a0d1229cebe470a9 (patch) | |
| tree | fff3d6f590833c0f894a6c7c300ab126b5259d95 /hw/ppc405_boards.c | |
| parent | 93102fd6010c68320bc9a008c8cf70cb4a36d4b9 (diff) | |
Introduce reset notifier order
Add the parameter 'order' to qemu_register_reset and sort callbacks on
registration. On system reset, callbacks with lower order will be
invoked before those with higher order. Update all existing users to the
standard order 0.
Note: At least for x86, the existing users seem to assume that handlers
are called in their registration order. Therefore, the patch preserves
this property. If someone feels bored, (s)he could try to identify this
dependency and express it properly on callback registration.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Diffstat (limited to 'hw/ppc405_boards.c')
| -rw-r--r-- | hw/ppc405_boards.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/ppc405_boards.c b/hw/ppc405_boards.c index 1ace32e6f7..a8f9a28105 100644 --- a/hw/ppc405_boards.c +++ b/hw/ppc405_boards.c @@ -165,7 +165,7 @@ static void ref405ep_fpga_init (uint32_t base) ref405ep_fpga_write, fpga); cpu_register_physical_memory(base, 0x00000100, fpga_memory); ref405ep_fpga_reset(fpga); - qemu_register_reset(&ref405ep_fpga_reset, fpga); + qemu_register_reset(&ref405ep_fpga_reset, 0, fpga); } static void ref405ep_init (ram_addr_t ram_size, @@ -483,7 +483,7 @@ static void taihu_cpld_init (uint32_t base) taihu_cpld_write, cpld); cpu_register_physical_memory(base, 0x00000100, cpld_memory); taihu_cpld_reset(cpld); - qemu_register_reset(&taihu_cpld_reset, cpld); + qemu_register_reset(&taihu_cpld_reset, 0, cpld); } static void taihu_405ep_init(ram_addr_t ram_size, |