diff options
| author | BALATON Zoltan <balaton@eik.bme.hu> | 2022-09-24 14:28:03 +0200 |
|---|---|---|
| committer | Daniel Henrique Barboza <danielhb413@gmail.com> | 2022-10-17 16:15:09 -0300 |
| commit | ef10aebb9a71f0c60f0b7aae808498333bb7bfd9 (patch) | |
| tree | fd50f47f16ab6726dcaad03da43dcca6a3dbdc3f /hw/ppc/sam460ex.c | |
| parent | 1e545fbc88bb5abe21553972a2244f272153476d (diff) | |
ppc440_sdram: Move RAM size check to ppc440_sdram_init
Move the check for valid memory sizes from board to sdram controller
init. This adds the missing valid memory sizes of 16 and 8 MiB to the
DoC and the board now only checks for additional restrictions imposed
by its firmware then sdram init checks for valid sizes for SoC.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <41da3797392acaacc7963b79512c8af8005fa4b0.1664021647.git.balaton@eik.bme.hu>
[danielhb: avoid 4*GiB size due to 32 bit build problems]
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Diffstat (limited to 'hw/ppc/sam460ex.c')
| -rw-r--r-- | hw/ppc/sam460ex.c | 32 |
1 files changed, 17 insertions, 15 deletions
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index b318521b01..13055a8916 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -74,13 +74,6 @@ #define EBC_FREQ 115000000 #define UART_FREQ 11059200 -/* The SoC could also handle 4 GiB but firmware does not work with that. */ -/* Maybe it overflows a signed 32 bit number somewhere? */ -static const ram_addr_t ppc460ex_sdram_bank_sizes[] = { - 2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * MiB, - 32 * MiB, 0 -}; - struct boot_info { uint32_t dt_base; uint32_t dt_size; @@ -273,7 +266,6 @@ static void sam460ex_init(MachineState *machine) { MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *isa = g_new(MemoryRegion, 1); - Ppc4xxSdramBank *ram_banks = g_new0(Ppc4xxSdramBank, 1); MemoryRegion *l2cache_ram = g_new(MemoryRegion, 1); DeviceState *uic[4]; int i; @@ -340,12 +332,22 @@ static void sam460ex_init(MachineState *machine) } /* SDRAM controller */ - /* put all RAM on first bank because board has one slot - * and firmware only checks that */ - ppc4xx_sdram_banks(machine->ram, 1, ram_banks, ppc460ex_sdram_bank_sizes); - + /* The SoC could also handle 4 GiB but firmware does not work with that. */ + if (machine->ram_size > 2 * GiB) { + error_report("Memory over 2 GiB is not supported"); + exit(1); + } + /* Firmware needs at least 64 MiB */ + if (machine->ram_size < 64 * MiB) { + error_report("Memory below 64 MiB is not supported"); + exit(1); + } + /* + * Put all RAM on first bank because board has one slot + * and firmware only checks that + */ + ppc440_sdram_init(env, 1, machine->ram); /* FIXME: does 460EX have ECC interrupts? */ - ppc440_sdram_init(env, 1, ram_banks); /* Enable SDRAM memory regions as we may boot without firmware */ ppc4xx_sdram_ddr2_enable(env); @@ -354,8 +356,8 @@ static void sam460ex_init(MachineState *machine) qdev_get_gpio_in(uic[0], 2)); i2c = PPC4xx_I2C(dev)->bus; /* SPD EEPROM on RAM module */ - spd_data = spd_data_generate(ram_banks->size < 128 * MiB ? DDR : DDR2, - ram_banks->size); + spd_data = spd_data_generate(machine->ram_size < 128 * MiB ? DDR : DDR2, + machine->ram_size); spd_data[20] = 4; /* SO-DIMM module */ smbus_eeprom_init_one(i2c, 0x50, spd_data); /* RTC */ |