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authorCédric Le Goater <clg@kaod.org>2022-08-17 17:08:29 +0200
committerDaniel Henrique Barboza <danielhb413@gmail.com>2022-08-31 14:08:06 -0300
commitda116a8aab47695a8364708f2e1d14ed6fcc659f (patch)
tree9d8b3fc8e9f78a7689c2ec4b01a9d3be30d82daa /hw/ppc/sam460ex.c
parent695bce07dc1c0f7de054fb471a494d572e649e07 (diff)
ppc/ppc405: QOM'ify MAL
The Memory Access Layer (MAL) controller is currently modeled as a DCR device with 4 IRQs. Also drop the ppc4xx_mal_init() helper and adapt the sam460ex machine. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> [balaton: ppc4xx_dcr_register changes, add finalize method] Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <d54a243dff94d95ba30dbcc09c27700a90ade932.1660746880.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Diffstat (limited to 'hw/ppc/sam460ex.c')
-rw-r--r--hw/ppc/sam460ex.c12
1 files changed, 8 insertions, 4 deletions
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index 31139c1554..c16303462d 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -280,7 +280,6 @@ static void sam460ex_init(MachineState *machine)
hwaddr ram_sizes[SDRAM_NR_BANKS] = {0};
MemoryRegion *l2cache_ram = g_new(MemoryRegion, 1);
DeviceState *uic[4];
- qemu_irq mal_irqs[4];
int i;
PCIBus *pci_bus;
PowerPCCPU *cpu;
@@ -387,10 +386,15 @@ static void sam460ex_init(MachineState *machine)
ppc4xx_sdr_init(env);
/* MAL */
- for (i = 0; i < ARRAY_SIZE(mal_irqs); i++) {
- mal_irqs[i] = qdev_get_gpio_in(uic[2], 3 + i);
+ dev = qdev_new(TYPE_PPC4xx_MAL);
+ qdev_prop_set_uint32(dev, "txc-num", 4);
+ qdev_prop_set_uint32(dev, "rxc-num", 16);
+ ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal);
+ object_unref(OBJECT(dev));
+ sbdev = SYS_BUS_DEVICE(dev);
+ for (i = 0; i < ARRAY_SIZE(PPC4xx_MAL(dev)->irqs); i++) {
+ sysbus_connect_irq(sbdev, i, qdev_get_gpio_in(uic[2], 3 + i));
}
- ppc4xx_mal_init(env, 4, 16, mal_irqs);
/* DMA */
ppc4xx_dma_init(env, 0x200);