diff options
author | Cédric Le Goater <clg@kaod.org> | 2022-08-17 17:08:20 +0200 |
---|---|---|
committer | Daniel Henrique Barboza <danielhb413@gmail.com> | 2022-08-31 14:08:06 -0300 |
commit | 4a7d2b7e5cebd00bdcc842517174ad33fd4934cb (patch) | |
tree | fe953067f4153747da8a2858f9bf2d2ecce1f666 /hw/ppc/ppc405.h | |
parent | 629cae617039e03d5bfdc0120ade69135a009d33 (diff) |
ppc/ppc405: QOM'ify CPC
The CPC controller is currently modeled as a DCR device.
Now that all clock settings are handled at the CPC level, change the
SoC "sys-clk" property to be an alias on the same property in the CPC
model.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[balaton: ppc4xx_dcr_register changes]
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <23393cb91a2c6c560a4461b3e9d1baa48ae28f74.1660746880.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Diffstat (limited to 'hw/ppc/ppc405.h')
-rw-r--r-- | hw/ppc/ppc405.h | 35 |
1 files changed, 34 insertions, 1 deletions
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index 8cc76cc8b3..2ba829988d 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -63,6 +63,39 @@ struct ppc4xx_bd_info_t { uint32_t bi_iic_fast[2]; }; +#define TYPE_PPC405_CPC "ppc405-cpc" +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405CpcState, PPC405_CPC); + +enum { + PPC405EP_CPU_CLK = 0, + PPC405EP_PLB_CLK = 1, + PPC405EP_OPB_CLK = 2, + PPC405EP_EBC_CLK = 3, + PPC405EP_MAL_CLK = 4, + PPC405EP_PCI_CLK = 5, + PPC405EP_UART0_CLK = 6, + PPC405EP_UART1_CLK = 7, + PPC405EP_CLK_NB = 8, +}; + +struct Ppc405CpcState { + Ppc4xxDcrDeviceState parent_obj; + + uint32_t sysclk; + clk_setup_t clk_setup[PPC405EP_CLK_NB]; + uint32_t boot; + uint32_t epctl; + uint32_t pllmr[2]; + uint32_t ucr; + uint32_t srr; + uint32_t jtagid; + uint32_t pci; + /* Clock and power management */ + uint32_t er; + uint32_t fr; + uint32_t sr; +}; + #define TYPE_PPC405_SOC "ppc405-soc" OBJECT_DECLARE_SIMPLE_TYPE(Ppc405SoCState, PPC405_SOC); @@ -78,9 +111,9 @@ struct Ppc405SoCState { MemoryRegion *dram_mr; hwaddr ram_size; - uint32_t sysclk; PowerPCCPU cpu; DeviceState *uic; + Ppc405CpcState cpc; }; /* PowerPC 405 core */ |