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| author | Cédric Le Goater <clg@kaod.org> | 2019-03-06 09:50:06 +0100 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2019-03-12 14:33:04 +1100 |
| commit | d514c48d41fba59ac492433071bad70c445db566 (patch) | |
| tree | cad9568114e4f36c4986a097cd22df529cf438a6 /hw/ppc/ppc.c | |
| parent | 7abb479c7abd1f03da09f34cd77d25ecf66aac82 (diff) | |
ppc/xive: hardwire the Physical CAM line of the thread context
By default on P9, the HW CAM line (23bits) is hardwired to :
0x000||0b1||4Bit chip number||7Bit Thread number.
When the block group mode is enabled at the controller level (PowerNV),
the CAM line is changed for CAM compares to :
4Bit chip number||0x001||7Bit Thread number
This will require changes in xive_presenter_tctx_match() possibly.
This is a lowlevel functionality of the HW controller and it is not
strictly needed. Leave it for later.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20190306085032.15744-2-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'hw/ppc/ppc.c')
0 files changed, 0 insertions, 0 deletions