ppc/pnv: Remove PnvLpcController::psi link

Create an anonymous output GPIO line to connect the LPC device with
the PSIHB device and raise the appropriate PSI IRQ line depending on
the processor model.

A temporary __pnv_psi_irq_set() routine is introduced to handle the
transition. It will be removed when all devices raising PSI interrupts
are converted to use GPIOs.

Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220323072846.1780212-3-clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>

1 files changed, 10 insertions, 0 deletions

diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
index c588a506c7..8b6298d4bd 100644
--- a/hw/ppc/pnv_psi.c
+++ b/hw/ppc/pnv_psi.c
@@ -216,6 +216,12 @@ void pnv_psi_irq_set(PnvPsi *psi, int irq, bool state)
     PNV_PSI_GET_CLASS(psi)->irq_set(psi, irq, state);
 }
 
+static void __pnv_psi_irq_set(void *opaque, int irq, int state)
+{
+    PnvPsi *psi = (PnvPsi *) opaque;
+    PNV_PSI_GET_CLASS(psi)->irq_set(psi, irq, state);
+}
+
 static void pnv_psi_power8_irq_set(PnvPsi *psi, int irq, bool state)
 {
     uint32_t xivr_reg;
@@ -512,6 +518,8 @@ static void pnv_psi_power8_realize(DeviceState *dev, Error **errp)
         ics_set_irq_type(ics, i, true);
     }
 
+    qdev_init_gpio_in(dev, __pnv_psi_irq_set, ics->nr_irqs);
+
     psi->qirqs = qemu_allocate_irqs(ics_set_irq, ics, ics->nr_irqs);
 
     /* XSCOM region for PSI registers */
@@ -873,6 +881,8 @@ static void pnv_psi_power9_realize(DeviceState *dev, Error **errp)
 
     psi->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc, xsrc->nr_irqs);
 
+    qdev_init_gpio_in(dev, __pnv_psi_irq_set, xsrc->nr_irqs);
+
     /* XSCOM region for PSI registers */
     pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_p9_xscom_ops,
                 psi, "xscom-psi", PNV9_XSCOM_PSIHB_SIZE);