diff options
| author | Nicholas Piggin <npiggin@gmail.com> | 2024-07-11 18:31:35 +1000 |
|---|---|---|
| committer | Nicholas Piggin <npiggin@gmail.com> | 2024-07-26 09:21:06 +1000 |
| commit | 16ffcb3401ddb991ec746de05595ba62eae45a1b (patch) | |
| tree | 2ecaa5ebb4886572c2efa7ffbd05f7ca802d09d3 /hw/ppc/pnv.c | |
| parent | 27f61d1b0b708b4659894cd0677f65ebed6eaa0b (diff) | |
ppc/pnv: Implement Power9 CPU core thread state indirect register
Power9 CPUs have a core thread state register accessible via SPRC/SPRD
indirect registers. This register includes a bit for big-core mode,
which skiboot requires.
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Diffstat (limited to 'hw/ppc/pnv.c')
0 files changed, 0 insertions, 0 deletions