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authorPeter Maydell <peter.maydell@linaro.org>2018-04-27 10:49:23 +0100
committerPeter Maydell <peter.maydell@linaro.org>2018-04-27 10:49:23 +0100
commitdcbd26f881557b83b99869b138b337feaf2d705d (patch)
tree5e607a9eb75393c5158a22ddde0ab532f52d5938 /hw/ppc/mac.h
parentca92651697bdb2f15b36d347a498fbc31f4a4893 (diff)
parent6233b679cae8741890f981c9dd6570d47715141e (diff)
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.13-20180427' into staging
ppc patch queue 2018-04-27 Here's the first batch of ppc patches for 2.13. This has a lot of stuff that's accumulated during the 2.12 freeze. Highlights are: * Many improvements for the Uninorth PCI host bridge for Mac machine types * Preliminary helpers improve handling of multiple backing pagesizes (not strictly ppc related, but have acks and aimed to allow future ppc changes) * Cleanups to pseries cpu initialization * Cleanups to hash64 MMU handling * Assorted bugfixes and improvements # gpg: Signature made Fri 27 Apr 2018 10:20:30 BST # gpg: using RSA key 6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-2.13-20180427: (49 commits) Clear mem_path if we fall back to anonymous RAM allocation spapr: Set compatibility mode before the rest of spapr_cpu_reset() target/ppc: Don't bother with MSR_EP in cpu_ppc_set_papr() spapr: Support ibm,dynamic-memory-v2 property ppc: e500: switch E500 based machines to full machine definition spapr: Add ibm,max-associativity-domains property target/ppc: Fold slb_nr into PPCHash64Options target/ppc: Get rid of POWERPC_MMU_VER() macros target/ppc: Remove unnecessary POWERPC_MMU_V3 flag from mmu_model target/ppc: Fold ci_large_pages flag into PPCHash64Options target/ppc: Move 1T segment and AMR options to PPCHash64Options target/ppc: Make hash64_opts field mandatory for 64-bit hash MMUs target/ppc: Split page size information into a separate allocation target/ppc: Move page size setup to helper function target/ppc: Remove fallback 64k pagesize information target/ppc: Avoid taking "env" parameter to mmu-hash64 functions target/ppc: Pass cpu instead of env to ppc_create_page_sizes_prop() target/ppc: Simplify cpu valid check in ppc_cpu_realize target/ppc: Standardize instance_init and realize function names spapr: drop useless dynamic sysbus device sanity check ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/ppc/mac.h')
-rw-r--r--hw/ppc/mac.h27
1 files changed, 14 insertions, 13 deletions
diff --git a/hw/ppc/mac.h b/hw/ppc/mac.h
index a02f797598..892dd03789 100644
--- a/hw/ppc/mac.h
+++ b/hw/ppc/mac.h
@@ -31,6 +31,8 @@
#include "hw/ide/internal.h"
#include "hw/input/adb.h"
#include "hw/misc/mos6522.h"
+#include "hw/pci/pci_host.h"
+#include "hw/pci-host/uninorth.h"
/* SMP is not enabled, for now */
#define MAX_CPUS 1
@@ -45,6 +47,14 @@
#define ESCC_CLOCK 3686400
+/* Old World IRQs */
+#define OLDWORLD_CUDA_IRQ 0x12
+#define OLDWORLD_ESCCB_IRQ 0x10
+#define OLDWORLD_ESCCA_IRQ 0xf
+#define OLDWORLD_IDE0_IRQ 0xd
+#define OLDWORLD_IDE0_DMA_IRQ 0x2
+#define OLDWORLD_IDE1_IRQ 0xe
+#define OLDWORLD_IDE1_DMA_IRQ 0x3
/* MacIO */
#define TYPE_MACIO_IDE "macio-ide"
@@ -75,23 +85,14 @@ void macio_ide_register_dma(MACIOIDEState *ide);
void macio_init(PCIDevice *dev,
MemoryRegion *pic_mem);
-/* Heathrow PIC */
-DeviceState *heathrow_pic_init(int nb_cpus, qemu_irq **irqs,
- qemu_irq **pic_irqs);
-
/* Grackle PCI */
#define TYPE_GRACKLE_PCI_HOST_BRIDGE "grackle-pcihost"
-PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic,
- MemoryRegion *address_space_mem,
- MemoryRegion *address_space_io);
/* UniNorth PCI */
-PCIBus *pci_pmac_init(qemu_irq *pic,
- MemoryRegion *address_space_mem,
- MemoryRegion *address_space_io);
-PCIBus *pci_pmac_u3_init(qemu_irq *pic,
- MemoryRegion *address_space_mem,
- MemoryRegion *address_space_io);
+UNINHostState *pci_pmac_init(qemu_irq *pic,
+ MemoryRegion *address_space_mem);
+UNINHostState *pci_pmac_u3_init(qemu_irq *pic,
+ MemoryRegion *address_space_mem);
/* Mac NVRAM */
#define TYPE_MACIO_NVRAM "macio-nvram"