diff options
author | Andreas Färber <afaerber@suse.de> | 2012-03-14 01:38:23 +0100 |
---|---|---|
committer | Andreas Färber <afaerber@suse.de> | 2012-03-14 22:20:26 +0100 |
commit | e2684c0b581f2742aa52edc8cd9be255032f9247 (patch) | |
tree | eef40085cd59e1c9be4f2b12986a2bf6d77d0efa /hw/ppc.h | |
parent | 61c56c8c862b8be9cb71faf74fcd990b3624aa41 (diff) |
ppc hw/: Don't use CPUState
Scripted conversion:
for file in hw/ppc*.[hc] hw/mpc8544_guts.c hw/spapr*.[hc] hw/virtex_ml507.c hw/xics.c; do
sed -i "s/CPUState/CPUPPCState/g" $file
done
Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Anthony Liguori <aliguori@us.ibm.com>
Diffstat (limited to 'hw/ppc.h')
-rw-r--r-- | hw/ppc.h | 28 |
1 files changed, 14 insertions, 14 deletions
@@ -1,4 +1,4 @@ -void ppc_set_irq (CPUState *env, int n_IRQ, int level); +void ppc_set_irq (CPUPPCState *env, int n_IRQ, int level); /* PowerPC hardware exceptions management helpers */ typedef void (*clk_setup_cb)(void *opaque, uint32_t freq); @@ -43,32 +43,32 @@ struct ppc_tb_t { */ uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset); -clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq); +clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq); /* Embedded PowerPC DCR management */ typedef uint32_t (*dcr_read_cb)(void *opaque, int dcrn); typedef void (*dcr_write_cb)(void *opaque, int dcrn, uint32_t val); -int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn), +int ppc_dcr_init (CPUPPCState *env, int (*dcr_read_error)(int dcrn), int (*dcr_write_error)(int dcrn)); -int ppc_dcr_register (CPUState *env, int dcrn, void *opaque, +int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque, dcr_read_cb drc_read, dcr_write_cb dcr_write); -clk_setup_cb ppc_40x_timers_init (CPUState *env, uint32_t freq, +clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq, unsigned int decr_excp); /* Embedded PowerPC reset */ -void ppc40x_core_reset (CPUState *env); -void ppc40x_chip_reset (CPUState *env); -void ppc40x_system_reset (CPUState *env); +void ppc40x_core_reset (CPUPPCState *env); +void ppc40x_chip_reset (CPUPPCState *env); +void ppc40x_system_reset (CPUPPCState *env); void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val); extern CPUWriteMemoryFunc * const PPC_io_write[]; extern CPUReadMemoryFunc * const PPC_io_read[]; void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val); -void ppc40x_irq_init (CPUState *env); -void ppce500_irq_init (CPUState *env); -void ppc6xx_irq_init (CPUState *env); -void ppc970_irq_init (CPUState *env); -void ppcPOWER7_irq_init (CPUState *env); +void ppc40x_irq_init (CPUPPCState *env); +void ppce500_irq_init (CPUPPCState *env); +void ppc6xx_irq_init (CPUPPCState *env); +void ppc970_irq_init (CPUPPCState *env); +void ppcPOWER7_irq_init (CPUPPCState *env); /* PPC machines for OpenBIOS */ enum { @@ -89,4 +89,4 @@ enum { #define PPC_SERIAL_MM_BAUDBASE 399193 /* ppc_booke.c */ -void ppc_booke_timers_init(CPUState *env, uint32_t freq, uint32_t flags); +void ppc_booke_timers_init(CPUPPCState *env, uint32_t freq, uint32_t flags); |