diff options
| author | Anthony Liguori <aliguori@us.ibm.com> | 2012-04-10 08:21:58 -0500 |
|---|---|---|
| committer | Anthony Liguori <aliguori@us.ibm.com> | 2012-04-10 08:21:58 -0500 |
| commit | 4e1957acc854b2f3f3068c75cef2a429f9b97011 (patch) | |
| tree | cab3ca24ed0fc963cb693c0d440a9495a2cc47eb /hw/pcie_port.c | |
| parent | 6da25bd5e8355230b9562417e386728c31783002 (diff) | |
| parent | ff71f2e8cacefae99179993204172bc65e4303df (diff) | |
Merge commit 'ff71f2e8cacefae99179993204172bc65e4303df' into staging
* commit 'ff71f2e8cacefae99179993204172bc65e4303df': (21 commits)
rtl8139: do the network/host communication only in normal operating mode
rtl8139: correctly check the opmode
net: move compute_mcast_idx() to net.h
rtl8139: support byte read to TxStatus registers
rtl8139: remove unused marco
rtl8139: limit transmission buffer size in c+ mode
pci_regs: Add PCI_EXP_TYPE_PCIE_BRIDGE
virtio-net: add DATA_VALID flag
pci_bridge: upper 32 bit are long registers
pci: fix bridge IO/BASE
pcie: drop functionality moved to core
pci: set memory type for memory behind the bridge
pci: add standard bridge device
slotid: add slot id capability
shpc: standard hot plug controller
pci_bridge: user-friendly default bus name
pci: make another unused extern function static
pci: don't export an internal function
pci_regs: Fix value of PCI_EXP_TYPE_RC_EC.
pci: Do not check if a bus exist in pci_parse_devaddr.
...
Diffstat (limited to 'hw/pcie_port.c')
| -rw-r--r-- | hw/pcie_port.c | 12 |
1 files changed, 1 insertions, 11 deletions
diff --git a/hw/pcie_port.c b/hw/pcie_port.c index 8a36f5cfc7..d6350e5e73 100644 --- a/hw/pcie_port.c +++ b/hw/pcie_port.c @@ -27,23 +27,13 @@ void pcie_port_init_reg(PCIDevice *d) pci_set_word(d->config + PCI_STATUS, 0); pci_set_word(d->config + PCI_SEC_STATUS, 0); - /* Unlike conventional pci bridge, some bits are hardwared to 0. */ + /* Unlike conventional pci bridge, some bits are hardwired to 0. */ pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_ISA | PCI_BRIDGE_CTL_VGA | PCI_BRIDGE_CTL_SERR | PCI_BRIDGE_CTL_BUS_RESET); - - /* 7.5.3.5 Prefetchable Memory Base Limit - * The Prefetchable Memory Base and Prefetchable Memory Limit registers - * must indicate that 64-bit addresses are supported, as defined in - * PCI-to-PCI Bridge Architecture Specification, Revision 1.2. - */ - pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE, - PCI_PREF_RANGE_TYPE_64); - pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT, - PCI_PREF_RANGE_TYPE_64); } /************************************************************************** |