diff options
| author | Michael S. Tsirkin <mst@redhat.com> | 2012-02-21 15:58:59 +0200 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2012-03-16 00:41:39 +0200 |
| commit | 633442ff56909214576549d34f5be1f50a67c5a6 (patch) | |
| tree | 91a6a0b7ac1affe7464de66c4e961c6fb5aba720 /hw/pcie_port.c | |
| parent | 15ab7a75335108c76700bea67602017fe305350d (diff) | |
pcie: drop functionality moved to core
Now that core sets memory type correctly,
remove this code from pcie port implementation.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'hw/pcie_port.c')
| -rw-r--r-- | hw/pcie_port.c | 12 |
1 files changed, 1 insertions, 11 deletions
diff --git a/hw/pcie_port.c b/hw/pcie_port.c index 8a36f5cfc7..d6350e5e73 100644 --- a/hw/pcie_port.c +++ b/hw/pcie_port.c @@ -27,23 +27,13 @@ void pcie_port_init_reg(PCIDevice *d) pci_set_word(d->config + PCI_STATUS, 0); pci_set_word(d->config + PCI_SEC_STATUS, 0); - /* Unlike conventional pci bridge, some bits are hardwared to 0. */ + /* Unlike conventional pci bridge, some bits are hardwired to 0. */ pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_ISA | PCI_BRIDGE_CTL_VGA | PCI_BRIDGE_CTL_SERR | PCI_BRIDGE_CTL_BUS_RESET); - - /* 7.5.3.5 Prefetchable Memory Base Limit - * The Prefetchable Memory Base and Prefetchable Memory Limit registers - * must indicate that 64-bit addresses are supported, as defined in - * PCI-to-PCI Bridge Architecture Specification, Revision 1.2. - */ - pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE, - PCI_PREF_RANGE_TYPE_64); - pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT, - PCI_PREF_RANGE_TYPE_64); } /************************************************************************** |