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authorLukas Stockner <lstockner@genesiscloud.com>2024-02-15 02:23:26 +0100
committerMichael S. Tsirkin <mst@redhat.com>2024-03-12 17:56:55 -0400
commitc08da86dc412cd44039bc78df02227578bc06268 (patch)
tree15ebe027e6b73719009fc52c3e830735315cb41b /hw/pci
parent52767e1063beaa17d59c739efd0b9c342923929d (diff)
pcie: Support PCIe Gen5/Gen6 link speeds
This patch extends the PCIe link speed option so that slots can be configured as supporting 32GT/s (Gen5) or 64GT/s (Gen5) speeds. This is as simple as setting the appropriate bit in LnkCap2 and the appropriate value in LnkCap and LnkCtl2. Signed-off-by: Lukas Stockner <lstockner@genesiscloud.com> Message-Id: <20240215012326.3272366-1-lstockner@genesiscloud.com> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'hw/pci')
-rw-r--r--hw/pci/pcie.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
index 6db0cf69cd..0b4817e144 100644
--- a/hw/pci/pcie.c
+++ b/hw/pci/pcie.c
@@ -153,6 +153,14 @@ static void pcie_cap_fill_slot_lnk(PCIDevice *dev)
pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP2,
PCI_EXP_LNKCAP2_SLS_16_0GB);
}
+ if (s->speed > QEMU_PCI_EXP_LNK_16GT) {
+ pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP2,
+ PCI_EXP_LNKCAP2_SLS_32_0GB);
+ }
+ if (s->speed > QEMU_PCI_EXP_LNK_32GT) {
+ pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP2,
+ PCI_EXP_LNKCAP2_SLS_64_0GB);
+ }
}
}