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authorpbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162>2006-09-24 17:01:44 +0000
committerpbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162>2006-09-24 17:01:44 +0000
commit80b3ada7dd56088613a446934d144a747e740fa1 (patch)
tree3dc8bf29b3bee0c06772b56e5add4a7d5df2de23 /hw/pci.c
parentd2b5931756fdb9f839180e33898cd1e3e4fbdc90 (diff)
Implement sun4u PCI IRQ routing.
Allow multiple PCI busses and PCI-PCI bridges. Fix bugs in Versatile PCI implementation. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2166 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/pci.c')
-rw-r--r--hw/pci.c103
1 files changed, 92 insertions, 11 deletions
diff --git a/hw/pci.c b/hw/pci.c
index 78f05cd90f..7c9db0e8d4 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -35,9 +35,11 @@ struct PCIBus {
SetIRQFunc *low_set_irq;
void *irq_opaque;
PCIDevice *devices[256];
+ PCIDevice *parent_dev;
+ PCIBus *next;
/* The bus IRQ state is the logical OR of the connected devices.
Keep a count of the number of devices with raised IRQs. */
- int irq_count[4];
+ int irq_count[];
};
static void pci_update_mappings(PCIDevice *d);
@@ -47,19 +49,29 @@ static int pci_irq_index;
static PCIBus *first_bus;
PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
- void *pic, int devfn_min)
+ void *pic, int devfn_min, int nirq)
{
PCIBus *bus;
- bus = qemu_mallocz(sizeof(PCIBus));
+ bus = qemu_mallocz(sizeof(PCIBus) + (nirq * sizeof(int)));
bus->set_irq = set_irq;
bus->map_irq = map_irq;
bus->irq_opaque = pic;
bus->devfn_min = devfn_min;
- memset(bus->irq_count, 0, sizeof(bus->irq_count));
first_bus = bus;
return bus;
}
+PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
+{
+ PCIBus *bus;
+ bus = qemu_mallocz(sizeof(PCIBus));
+ bus->map_irq = map_irq;
+ bus->parent_dev = dev;
+ bus->next = dev->bus->next;
+ dev->bus->next = bus;
+ return bus;
+}
+
int pci_bus_num(PCIBus *s)
{
return s->bus_num;
@@ -351,7 +363,9 @@ void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
addr, val, len);
#endif
bus_num = (addr >> 16) & 0xff;
- if (bus_num != 0)
+ while (s && s->bus_num != bus_num)
+ s = s->next;
+ if (!s)
return;
pci_dev = s->devices[(addr >> 8) & 0xff];
if (!pci_dev)
@@ -372,7 +386,9 @@ uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
uint32_t val;
bus_num = (addr >> 16) & 0xff;
- if (bus_num != 0)
+ while (s && s->bus_num != bus_num)
+ s= s->next;
+ if (!s)
goto fail;
pci_dev = s->devices[(addr >> 8) & 0xff];
if (!pci_dev) {
@@ -411,11 +427,21 @@ uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
/* 0 <= irq_num <= 3. level must be 0 or 1 */
void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level)
{
- PCIBus *bus = pci_dev->bus;
+ PCIBus *bus;
+ int change;
+
+ change = level - pci_dev->irq_state[irq_num];
+ if (!change)
+ return;
- irq_num = bus->map_irq(pci_dev, irq_num);
- bus->irq_count[irq_num] += level - pci_dev->irq_state[irq_num];
pci_dev->irq_state[irq_num] = level;
+ bus = pci_dev->bus;
+ while (!bus->set_irq) {
+ irq_num = bus->map_irq(pci_dev, irq_num);
+ pci_dev = bus->parent_dev;
+ bus = pci_dev->bus;
+ }
+ bus->irq_count[irq_num] += change;
bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
}
@@ -465,6 +491,9 @@ static void pci_info_device(PCIDevice *d)
if (d->config[PCI_INTERRUPT_PIN] != 0) {
term_printf(" IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
}
+ if (class == 0x0604) {
+ term_printf(" BUS %d.\n", d->config[0x19]);
+ }
for(i = 0;i < PCI_NUM_REGIONS; i++) {
r = &d->io_regions[i];
if (r->size != 0) {
@@ -478,14 +507,19 @@ static void pci_info_device(PCIDevice *d)
}
}
}
+ if (class == 0x0604 && d->config[0x19] != 0) {
+ pci_for_each_device(d->config[0x19], pci_info_device);
+ }
}
-void pci_for_each_device(void (*fn)(PCIDevice *d))
+void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
{
PCIBus *bus = first_bus;
PCIDevice *d;
int devfn;
+ while (bus && bus->bus_num != bus_num)
+ bus = bus->next;
if (bus) {
for(devfn = 0; devfn < 256; devfn++) {
d = bus->devices[devfn];
@@ -497,7 +531,7 @@ void pci_for_each_device(void (*fn)(PCIDevice *d))
void pci_info(void)
{
- pci_for_each_device(pci_info_device);
+ pci_for_each_device(0, pci_info_device);
}
/* Initialize a PCI NIC. */
@@ -515,3 +549,50 @@ void pci_nic_init(PCIBus *bus, NICInfo *nd)
}
}
+typedef struct {
+ PCIDevice dev;
+ PCIBus *bus;
+} PCIBridge;
+
+void pci_bridge_write_config(PCIDevice *d,
+ uint32_t address, uint32_t val, int len)
+{
+ PCIBridge *s = (PCIBridge *)d;
+
+ if (address == 0x19 || (address == 0x18 && len > 1)) {
+ if (address == 0x19)
+ s->bus->bus_num = val & 0xff;
+ else
+ s->bus->bus_num = (val >> 8) & 0xff;
+#if defined(DEBUG_PCI)
+ printf ("pci-bridge: %s: Assigned bus %d\n", d->name, s->bus->bus_num);
+#endif
+ }
+ pci_default_write_config(d, address, val, len);
+}
+
+PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
+ pci_map_irq_fn map_irq, const char *name)
+{
+ PCIBridge *s;
+ s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
+ devfn, NULL, pci_bridge_write_config);
+ s->dev.config[0x00] = id >> 16;
+ s->dev.config[0x01] = id > 24;
+ s->dev.config[0x02] = id; // device_id
+ s->dev.config[0x03] = id >> 8;
+ s->dev.config[0x04] = 0x06; // command = bus master, pci mem
+ s->dev.config[0x05] = 0x00;
+ s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
+ s->dev.config[0x07] = 0x00; // status = fast devsel
+ s->dev.config[0x08] = 0x00; // revision
+ s->dev.config[0x09] = 0x00; // programming i/f
+ s->dev.config[0x0A] = 0x04; // class_sub = PCI to PCI bridge
+ s->dev.config[0x0B] = 0x06; // class_base = PCI_bridge
+ s->dev.config[0x0D] = 0x10; // latency_timer
+ s->dev.config[0x0E] = 0x81; // header_type
+ s->dev.config[0x1E] = 0xa0; // secondary status
+
+ s->bus = pci_register_secondary_bus(&s->dev, map_irq);
+ return s->bus;
+}