diff options
| author | Cédric Le Goater <clg@kaod.org> | 2022-03-02 06:51:39 +0100 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2022-03-02 06:51:39 +0100 |
| commit | 0aa2612a01f233a4a25fb89e8362baf6cf896be6 (patch) | |
| tree | 843c92a177ce54f209f8f069fa35aa3405d5f938 /hw/pci-host | |
| parent | aadf13abaad43dd1f8b6113e516649578af63775 (diff) | |
ppc/xive: Add support for PQ state bits offload
The trigger message coming from a HW source contains a special bit
informing the XIVE interrupt controller that the PQ bits have been
checked at the source or not. Depending on the value, the IC can
perform the check and the state transition locally using its own PQ
state bits.
The following changes add new accessors to the XiveRouter required to
query and update the PQ state bits. This only applies to the PowerNV
machine. sPAPR accessors are provided but the pSeries machine should
not be concerned by such complex configuration for the moment.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'hw/pci-host')
| -rw-r--r-- | hw/pci-host/pnv_phb4.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index 5344a6d4a6..58498feace 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -1660,14 +1660,19 @@ static const char *pnv_phb4_root_bus_path(PCIHostState *host_bridge, return phb->bus_path; } -static void pnv_phb4_xive_notify(XiveNotifier *xf, uint32_t srcno) +static void pnv_phb4_xive_notify(XiveNotifier *xf, uint32_t srcno, + bool pq_checked) { PnvPHB4 *phb = PNV_PHB4(xf); uint64_t notif_port = phb->regs[PHB_INT_NOTIFY_ADDR >> 3]; uint32_t offset = phb->regs[PHB_INT_NOTIFY_INDEX >> 3]; - uint64_t data = XIVE_TRIGGER_PQ | offset | srcno; + uint64_t data = offset | srcno; MemTxResult result; + if (pq_checked) { + data |= XIVE_TRIGGER_PQ; + } + trace_pnv_phb4_xive_notify(notif_port, data); address_space_stq_be(&address_space_memory, notif_port, data, |