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authorMark Cave-Ayland <mark.cave-ayland@ilande.co.uk>2017-12-21 07:32:57 +0000
committerMark Cave-Ayland <mark.cave-ayland@ilande.co.uk>2018-01-09 21:48:19 +0000
commit33c5eb02c4f51515896a5a13cb68f6f01ce8d0af (patch)
treec70f9ed9c5c313a623d9340dd30f4f061fe5382c /hw/pci-host
parentd9e4d6829c14d3e3d71906b0dc7e7ec9a77654bf (diff)
apb: remove busA property from PBMPCIBridge state
Since the previous commit the only remaining use of the qdev busA property is to configure the PCI bridge in front of the onboard ebus devices differently to allow early OpenBIOS serial console access. Instead we can now manually update the PCI configuration for bridge A in pci_pbm_reset() and thus completely remove the busA property from the PBMPCIBridge state. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Artyom Tarasenko <atar4qemu@gmail.com>
Diffstat (limited to 'hw/pci-host')
-rw-r--r--hw/pci-host/apb.c29
1 files changed, 13 insertions, 16 deletions
diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c
index 8bdbbfd214..5562f1adfd 100644
--- a/hw/pci-host/apb.c
+++ b/hw/pci-host/apb.c
@@ -581,18 +581,11 @@ static void apb_pci_bridge_realize(PCIDevice *dev, Error **errp)
* the reset value should be zero unless the boot pin is tied high
* (which is true) and thus it should be PCI_COMMAND_MEMORY.
*/
- uint16_t cmd = PCI_COMMAND_MEMORY;
PBMPCIBridge *br = PBM_PCI_BRIDGE(dev);
pci_bridge_initfn(dev, TYPE_PCI_BUS);
- /* If initialising busA, ensure that we allow IO transactions so that
- we get the early serial console until OpenBIOS configures the bridge */
- if (br->busA) {
- cmd |= PCI_COMMAND_IO;
- }
-
- pci_set_word(dev->config + PCI_COMMAND, cmd);
+ pci_set_word(dev->config + PCI_COMMAND, PCI_COMMAND_MEMORY);
pci_set_word(dev->config + PCI_STATUS,
PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
PCI_STATUS_DEVSEL_MEDIUM);
@@ -608,8 +601,10 @@ static void apb_pci_bridge_realize(PCIDevice *dev, Error **errp)
static void pci_pbm_reset(DeviceState *d)
{
- unsigned int i;
APBState *s = APB_DEVICE(d);
+ PCIDevice *pci_dev;
+ unsigned int i;
+ uint16_t cmd;
for (i = 0; i < 8; i++) {
s->pci_irq_map[i] &= PBM_PCI_IMR_MASK;
@@ -625,6 +620,15 @@ static void pci_pbm_reset(DeviceState *d)
/* Power on reset */
s->reset_control = POR;
}
+
+ /* As this is the busA PCI bridge which contains the on-board devices
+ * attached to the ebus, ensure that we initially allow IO transactions
+ * so that we get the early serial console until OpenBIOS can properly
+ * configure the PCI bridge itself */
+ pci_dev = PCI_DEVICE(s->bridgeA);
+ cmd = pci_get_word(pci_dev->config + PCI_COMMAND);
+ pci_set_word(pci_dev->config + PCI_COMMAND, cmd | PCI_COMMAND_IO);
+ pci_bridge_update_mappings(PCI_BRIDGE(pci_dev));
}
static const MemoryRegionOps pci_config_ops = {
@@ -681,7 +685,6 @@ static void pci_pbm_realize(DeviceState *dev, Error **errp)
TYPE_PBM_PCI_BRIDGE);
s->bridgeA = PCI_BRIDGE(pci_dev);
pci_bridge_map_irq(s->bridgeA, "pciA", pci_pbmA_map_irq);
- qdev_prop_set_bit(DEVICE(pci_dev), "busA", true);
qdev_init_nofail(&pci_dev->qdev);
}
@@ -783,11 +786,6 @@ static const TypeInfo pbm_host_info = {
.class_init = pbm_host_class_init,
};
-static Property pbm_pci_properties[] = {
- DEFINE_PROP_BOOL("busA", PBMPCIBridge, busA, false),
- DEFINE_PROP_END_OF_LIST(),
-};
-
static void pbm_pci_bridge_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -803,7 +801,6 @@ static void pbm_pci_bridge_class_init(ObjectClass *klass, void *data)
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
dc->reset = pci_bridge_reset;
dc->vmsd = &vmstate_pci_device;
- dc->props = pbm_pci_properties;
}
static const TypeInfo pbm_pci_bridge_info = {