diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2014-08-18 12:55:02 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-08-18 12:55:02 +0100 |
| commit | 08ab59770da57648bfb8fc9be37f0ef7fb50b0f9 (patch) | |
| tree | b6840a4ace1a8d7f45dbc0ec9991aa42384d0204 /hw/pci-host | |
| parent | da398fcc256b226217c92c8a83abf3a6ff247e8b (diff) | |
| parent | 2a5fade753e66ae68f0131962391cd78b99afa53 (diff) | |
Merge remote-tracking branch 'remotes/mcayland/qemu-sparc' into staging
* remotes/mcayland/qemu-sparc:
target-sparc64: implement Short Floating-Point Store Instructions
apb: add IOMMU flush register implementation
sun4u: switch second PCI-ebus bridge BAR over to PCI IO space
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/pci-host')
| -rw-r--r-- | hw/pci-host/apb.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c index d238a84f95..60bd81e477 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/apb.c @@ -94,6 +94,7 @@ do { printf("IOMMU: " fmt , ## __VA_ARGS__); } while (0) #define IOMMU_CTRL_TSB_SHIFT 16 #define IOMMU_BASE 0x8 +#define IOMMU_FLUSH 0x10 #define IOMMU_TTE_DATA_V (1ULL << 63) #define IOMMU_TTE_DATA_SIZE (1ULL << 61) @@ -352,6 +353,9 @@ static void iommu_config_write(void *opaque, hwaddr addr, is->regs[IOMMU_BASE >> 3] &= 0xffffffff00000000ULL; is->regs[IOMMU_BASE >> 3] |= val & 0xffffffffULL; break; + case IOMMU_FLUSH: + case IOMMU_FLUSH + 0x4: + break; default: qemu_log_mask(LOG_UNIMP, "apb iommu: Unimplemented register write " @@ -387,6 +391,10 @@ static uint64_t iommu_config_read(void *opaque, hwaddr addr, unsigned size) case IOMMU_BASE + 0x4: val = is->regs[IOMMU_BASE >> 3] & 0xffffffffULL; break; + case IOMMU_FLUSH: + case IOMMU_FLUSH + 0x4: + val = 0; + break; default: qemu_log_mask(LOG_UNIMP, "apb iommu: Unimplemented register read " @@ -415,7 +423,7 @@ static void apb_config_writel (void *opaque, hwaddr addr, /* XXX: not implemented yet */ break; case 0x200 ... 0x217: /* IOMMU */ - iommu_config_write(is, (addr & 0xf), val, size); + iommu_config_write(is, (addr & 0x1f), val, size); break; case 0xc00 ... 0xc3f: /* PCI interrupt control */ if (addr & 4) { @@ -497,7 +505,7 @@ static uint64_t apb_config_readl (void *opaque, /* XXX: not implemented yet */ break; case 0x200 ... 0x217: /* IOMMU */ - val = iommu_config_read(is, (addr & 0xf), size); + val = iommu_config_read(is, (addr & 0x1f), size); break; case 0xc00 ... 0xc3f: /* PCI interrupt control */ if (addr & 4) { |