aboutsummaryrefslogtreecommitdiff
path: root/hw/pci-host/pnv_phb4.c
diff options
context:
space:
mode:
authorCédric Le Goater <clg@kaod.org>2022-03-02 06:51:39 +0100
committerCédric Le Goater <clg@kaod.org>2022-03-02 06:51:39 +0100
commit623575e16cd55082ca36b57114a774f146b2c95b (patch)
treed75205ae6db121b3518f6937eac1722145f044ce /hw/pci-host/pnv_phb4.c
parentae4c68e366d68058cd50318d1716fb59c63f4907 (diff)
ppc/pnv: Add model for POWER10 PHB5 PCIe Host bridge
PHB4 and PHB5 are very similar. Use the PHB4 models with some minor adjustements in a subclass for P10. Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'hw/pci-host/pnv_phb4.c')
-rw-r--r--hw/pci-host/pnv_phb4.c20
1 files changed, 20 insertions, 0 deletions
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index 846e7d0c3e..5344a6d4a6 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -1812,9 +1812,29 @@ static const TypeInfo pnv_phb4_root_port_info = {
.class_init = pnv_phb4_root_port_class_init,
};
+static void pnv_phb5_root_port_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+ dc->desc = "IBM PHB5 PCIE Root Port";
+ dc->user_creatable = true;
+
+ k->vendor_id = PCI_VENDOR_ID_IBM;
+ k->device_id = PNV_PHB5_DEVICE_ID;
+}
+
+static const TypeInfo pnv_phb5_root_port_info = {
+ .name = TYPE_PNV_PHB5_ROOT_PORT,
+ .parent = TYPE_PNV_PHB4_ROOT_PORT,
+ .instance_size = sizeof(PnvPHB4RootPort),
+ .class_init = pnv_phb5_root_port_class_init,
+};
+
static void pnv_phb4_register_types(void)
{
type_register_static(&pnv_phb4_root_bus_info);
+ type_register_static(&pnv_phb5_root_port_info);
type_register_static(&pnv_phb4_root_port_info);
type_register_static(&pnv_phb4_type_info);
type_register_static(&pnv_phb4_iommu_memory_region_info);