diff options
| author | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2022-06-16 15:51:25 +0100 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2022-06-16 12:54:57 -0400 |
| commit | 18cef1c6a5a37710a2e5876fed2445849f31e321 (patch) | |
| tree | a89e89a03c491f4f9c83e020b61e639dddf61091 /hw/pci-bridge/meson.build | |
| parent | 638b752da30a9daffb0c92166937a0cb777f9e23 (diff) | |
pci-bridge/cxl_downstream: Add a CXL switch downstream port
Emulation of a simple CXL Switch downstream port.
The Device ID has been allocated for this use.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20220616145126.8002-3-Jonathan.Cameron@huawei.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'hw/pci-bridge/meson.build')
| -rw-r--r-- | hw/pci-bridge/meson.build | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/pci-bridge/meson.build b/hw/pci-bridge/meson.build index 6828f0e08d..243ceeda50 100644 --- a/hw/pci-bridge/meson.build +++ b/hw/pci-bridge/meson.build @@ -6,7 +6,7 @@ pci_ss.add(when: 'CONFIG_PCIE_PORT', if_true: files('pcie_root_port.c', 'gen_pci pci_ss.add(when: 'CONFIG_PXB', if_true: files('pci_expander_bridge.c'), if_false: files('pci_expander_bridge_stubs.c')) pci_ss.add(when: 'CONFIG_XIO3130', if_true: files('xio3130_upstream.c', 'xio3130_downstream.c')) -pci_ss.add(when: 'CONFIG_CXL', if_true: files('cxl_root_port.c', 'cxl_upstream.c')) +pci_ss.add(when: 'CONFIG_CXL', if_true: files('cxl_root_port.c', 'cxl_upstream.c', 'cxl_downstream.c')) # NewWorld PowerMac pci_ss.add(when: 'CONFIG_DEC_PCI', if_true: files('dec.c')) |