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authorHavard Skinnemoen <hskinnemoen@google.com>2020-10-23 14:06:37 -0700
committerPeter Maydell <peter.maydell@linaro.org>2020-10-27 11:10:32 +0000
commit526dbbe087475599589ada4df70a337c09ae0f3f (patch)
treee952fde2b6f45bb9bdb891998a9fa71c16b0bb67 /hw/pci-bridge/dec.h
parente23e7b12594ec0804c2d9f509f71841c82a62d1c (diff)
hw/gpio: Add GPIO model for Nuvoton NPCM7xx
The NPCM7xx chips have multiple GPIO controllers that are mostly identical except for some minor differences like the reset values of some registers. Each controller controls up to 32 pins. Each individual pin is modeled as a pair of unnamed GPIOs -- one for emitting the actual pin state, and one for driving the pin externally. Like the nRF51 GPIO controller, a gpio level may be negative, which means the pin is not driven, or floating. Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/pci-bridge/dec.h')
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