diff options
| author | Jan Kiszka <jan.kiszka@siemens.com> | 2011-10-16 23:25:49 +0200 |
|---|---|---|
| committer | Jan Kiszka <jan.kiszka@siemens.com> | 2012-01-19 12:14:42 +0100 |
| commit | a39c1d47ac970312333bb93456e249e965315490 (patch) | |
| tree | 4085333d4bc0640be8ee3f52ad0fd20e73815ee7 /hw/pc_piix.c | |
| parent | 10b618827507fbdbe7cf1a9b1f2c81d254dcd8b8 (diff) | |
kvm: x86: Add user space part for in-kernel IOAPIC
This introduces the KVM-accelerated IOAPIC model 'kvm-ioapic' and
extends the IRQ routing setup by the 0->2 redirection when needed.
The kvm-ioapic model has a property that allows to define its GSI base
for injecting interrupts into the kernel model. This will allow to
disentangle PIC and IOAPIC pins for chipsets that support more
sophisticated IRQ routes than the PIIX3. So far the base is kept at 0,
i.e. PIC and IOAPIC share pins 0..15.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Diffstat (limited to 'hw/pc_piix.c')
| -rw-r--r-- | hw/pc_piix.c | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/hw/pc_piix.c b/hw/pc_piix.c index 297c04a9ab..a285ad25f8 100644 --- a/hw/pc_piix.c +++ b/hw/pc_piix.c @@ -69,6 +69,15 @@ static void kvm_piix3_setup_irq_routing(bool pci_enabled) for (i = 8; i < 16; ++i) { kvm_irqchip_add_route(s, i, KVM_IRQCHIP_PIC_SLAVE, i - 8); } + if (pci_enabled) { + for (i = 0; i < 24; ++i) { + if (i == 0) { + kvm_irqchip_add_route(s, i, KVM_IRQCHIP_IOAPIC, 2); + } else if (i != 2) { + kvm_irqchip_add_route(s, i, KVM_IRQCHIP_IOAPIC, i); + } + } + } ret = kvm_irqchip_commit_routes(s); if (ret < 0) { hw_error("KVM IRQ routing setup failed"); @@ -95,7 +104,11 @@ static void ioapic_init(GSIState *gsi_state) SysBusDevice *d; unsigned int i; - dev = qdev_create(NULL, "ioapic"); + if (kvm_enabled() && kvm_irqchip_in_kernel()) { + dev = qdev_create(NULL, "kvm-ioapic"); + } else { + dev = qdev_create(NULL, "ioapic"); + } qdev_init_nofail(dev); d = sysbus_from_qdev(dev); sysbus_mmio_map(d, 0, 0xfec00000); |