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authorJan Kiszka <jan.kiszka@siemens.com>2009-05-02 00:29:37 +0200
committerAnthony Liguori <aliguori@us.ibm.com>2009-05-22 10:50:34 -0500
commit8217606e6edb49591b4a6fd5a0d1229cebe470a9 (patch)
treefff3d6f590833c0f894a6c7c300ab126b5259d95 /hw/pc.c
parent93102fd6010c68320bc9a008c8cf70cb4a36d4b9 (diff)
Introduce reset notifier order
Add the parameter 'order' to qemu_register_reset and sort callbacks on registration. On system reset, callbacks with lower order will be invoked before those with higher order. Update all existing users to the standard order 0. Note: At least for x86, the existing users seem to assume that handlers are called in their registration order. Therefore, the patch preserves this property. If someone feels bored, (s)he could try to identify this dependency and express it properly on callback registration. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Diffstat (limited to 'hw/pc.c')
-rw-r--r--hw/pc.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/pc.c b/hw/pc.c
index e9682fadf2..faaa60fe8c 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -81,7 +81,7 @@ static void option_rom_setup_reset(target_phys_addr_t addr, unsigned size)
cpu_physical_memory_read(addr, rrd->data, size);
rrd->addr = addr;
rrd->size = size;
- qemu_register_reset(option_rom_reset, rrd);
+ qemu_register_reset(option_rom_reset, 0, rrd);
}
static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
@@ -875,7 +875,7 @@ static void pc_init1(ram_addr_t ram_size,
/* XXX: enable it in all cases */
env->cpuid_features |= CPUID_APIC;
}
- qemu_register_reset(main_cpu_reset, env);
+ qemu_register_reset(main_cpu_reset, 0, env);
if (pci_enabled) {
apic_init(env);
}