diff options
| author | Scott Wood <scottwood@freescale.com> | 2012-12-13 16:12:03 +0000 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2013-01-07 17:37:08 +0100 |
| commit | 0d4046833ba44c5f29e5dcce2dde0a6202225e59 (patch) | |
| tree | e2c9c6a71b54e63a616c126e1a819efd71aa7451 /hw/openpic.c | |
| parent | 0fe04622c11a4f131070196ad5cd97ce94d9c33b (diff) | |
openpic: BRR1 is not a CPU-specific register.
It's in the address range that normally contains a magic redirection
to the CPU-specific region of the curretn CPU, but it isn't actually
a per-CPU register. On real hardware BRR1 shows up only at 0x40000,
not at 0x60000 or other non-magic per-CPU areas. Plus, this makes
it possible to read the register on the QEMU command line with "xp".
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'hw/openpic.c')
| -rw-r--r-- | hw/openpic.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/hw/openpic.c b/hw/openpic.c index f0877fae5e..337dbf5a44 100644 --- a/hw/openpic.c +++ b/hw/openpic.c @@ -587,6 +587,8 @@ static uint64_t openpic_gbl_read(void *opaque, hwaddr addr, unsigned len) retval = 0x00000000; break; case 0x00: /* Block Revision Register1 (BRR1) */ + retval = opp->brr1; + break; case 0x40: case 0x50: case 0x60: @@ -878,9 +880,6 @@ static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr, dst = &opp->dst[idx]; addr &= 0xFF0; switch (addr) { - case 0x00: /* Block Revision Register1 (BRR1) */ - retval = opp->brr1; - break; case 0x80: /* PCTP */ retval = dst->pctp; break; |