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authorPeter Maydell <peter.maydell@linaro.org>2023-07-17 11:05:08 +0100
committerPeter Maydell <peter.maydell@linaro.org>2023-07-17 11:05:08 +0100
commite60a7d0d4d89c8bca8a74a877e31abce50e848e3 (patch)
treea90b3ccc1de5c33477bd0993be9d57856854b643 /hw/nvram/xlnx-efuse.c
parenteeb9578c36e78af6ee661f491e3f8744b1e0b6fb (diff)
accel/tcg: Zero-pad PC in TCG CPU exec trace lines
In commit f0a08b0913befbd we changed the type of the PC from target_ulong to vaddr. In doing so we inadvertently dropped the zero-padding on the PC in trace lines (the second item inside the [] in these lines). They used to look like this on AArch64, for instance: Trace 0: 0x7f2260000100 [00000000/0000000040000000/00000061/ff200000] and now they look like this: Trace 0: 0x7f4f50000100 [00000000/40000000/00000061/ff200000] and if the PC happens to be somewhere low like 0x5000 then the field is shown as /5000/. This is because TARGET_FMT_lx is a "%08x" or "%016x" specifier, depending on TARGET_LONG_SIZE, whereas VADDR_PRIx is just PRIx64 with no width specifier. Restore the zero-padding by adding an 016 width specifier to this tracing and a couple of others that were similarly recently changed to use VADDR_PRIx without a width specifier. We can't unfortunately restore the "32-bit guests are padded to 8 hex digits and 64-bit guests to 16 hex digits" behaviour so easily. Fixes: f0a08b0913befbd ("accel/tcg/cpu-exec.c: Widen pc to vaddr") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-id: 20230711165434.4123674-1-peter.maydell@linaro.org
Diffstat (limited to 'hw/nvram/xlnx-efuse.c')
0 files changed, 0 insertions, 0 deletions