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authorKlaus Jensen <k.jensen@samsung.com>2022-11-09 11:40:16 +0100
committerMichael Tokarev <mjt@tls.msk.ru>2024-03-14 21:24:34 +0300
commit5c3889be15676d7071d5458c1f055bf0871c4300 (patch)
tree86b37378012afb917c3c2064253c83e505ec5fba /hw/nvme/ctrl.c
parent201c9701f58cd02e86de249d9dcf01dfc71c4cb1 (diff)
hw/nvme: cleanup error reporting in nvme_init_pci()
Replace the local Error variable with errp and ERRP_GUARD() and change the return value to bool. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Klaus Jensen <k.jensen@samsung.com> (cherry picked from commit 973f76cf7743545a5d8a0a8bfdfe2cd02aa3e238) Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> (Mjt: needed for v8.2.0-2319-gfa905f65c5 "hw/nvme: add machine compatibility parameter to enable msix exclusive bar")
Diffstat (limited to 'hw/nvme/ctrl.c')
-rw-r--r--hw/nvme/ctrl.c25
1 files changed, 12 insertions, 13 deletions
diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
index 75180823a6..f2b308f5fa 100644
--- a/hw/nvme/ctrl.c
+++ b/hw/nvme/ctrl.c
@@ -7288,15 +7288,14 @@ static int nvme_add_pm_capability(PCIDevice *pci_dev, uint8_t offset)
return 0;
}
-static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp)
+static bool nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp)
{
+ ERRP_GUARD();
uint8_t *pci_conf = pci_dev->config;
uint64_t bar_size;
unsigned msix_table_offset, msix_pba_offset;
int ret;
- Error *err = NULL;
-
pci_conf[PCI_INTERRUPT_PIN] = 1;
pci_config_set_prog_interface(pci_conf, 0x2);
@@ -7333,14 +7332,14 @@ static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp)
}
ret = msix_init(pci_dev, n->params.msix_qsize,
&n->bar0, 0, msix_table_offset,
- &n->bar0, 0, msix_pba_offset, 0, &err);
- if (ret < 0) {
- if (ret == -ENOTSUP) {
- warn_report_err(err);
- } else {
- error_propagate(errp, err);
- return ret;
- }
+ &n->bar0, 0, msix_pba_offset, 0, errp);
+ if (ret == -ENOTSUP) {
+ /* report that msix is not supported, but do not error out */
+ warn_report_err(*errp);
+ *errp = NULL;
+ } else if (ret < 0) {
+ /* propagate error to caller */
+ return false;
}
nvme_update_msixcap_ts(pci_dev, n->conf_msix_qsize);
@@ -7357,7 +7356,7 @@ static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp)
nvme_init_sriov(n, pci_dev, 0x120);
}
- return 0;
+ return true;
}
static void nvme_init_subnqn(NvmeCtrl *n)
@@ -7533,7 +7532,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp)
return;
}
nvme_init_state(n);
- if (nvme_init_pci(n, pci_dev, errp)) {
+ if (!nvme_init_pci(n, pci_dev, errp)) {
return;
}
nvme_init_ctrl(n, pci_dev);