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authorPeter Maydell <peter.maydell@linaro.org>2020-11-29 17:40:20 +0000
committerPeter Maydell <peter.maydell@linaro.org>2020-12-15 12:04:30 +0000
commitcd2528de2cd07d790949c1b5532ae2ab11255e1b (patch)
treebf88c1659d60c1a88632cda66cb43c6aeaf507cf /hw/nios2/10m50_devboard.c
parent71b3254dd227f4c5e0a1a4005175a98e0a2cdc19 (diff)
target/nios2: Move IIC code into CPU object proper
The Nios2 architecture supports two different interrupt controller options: * The IIC (Internal Interrupt Controller) is part of the CPU itself; it has 32 IRQ input lines and no NMI support. Interrupt status is queried and controlled via the CPU's ipending and istatus registers. * The EIC (External Interrupt Controller) interface allows the CPU to connect to an external interrupt controller. The interface allows the interrupt controller to present a packet of information containing: - handler address - interrupt level - register set - NMI mode QEMU does not model an EIC currently. We do model the IIC, but its implementation is split across code in hw/nios2/cpu_pic.c and hw/intc/nios2_iic.c. The code in those two files has no state of its own -- the IIC state is in the Nios2CPU state struct. Because CPU objects now inherit (indirectly) from TYPE_DEVICE, they can have GPIO input lines themselves, so we can implement the IIC directly in the CPU object the same way that real hardware does. Create named "IRQ" GPIO inputs to the Nios2 CPU object, and make the only user of the IIC wire up directly to those instead. Note that the old code had an "NMI" concept which was entirely unused and also as far as I can see not architecturally correct, since only the EIC has a concept of an NMI. This fixes a Coverity-reported trivial memory leak of the IRQ array allocated in nios2_cpu_pic_init(). Fixes: Coverity CID 1421916 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201129174022.26530-2-peter.maydell@linaro.org Reviewed-by: Wentong Wu <wentong.wu@intel.com> Tested-by: Wentong Wu <wentong.wu@intel.com>
Diffstat (limited to 'hw/nios2/10m50_devboard.c')
-rw-r--r--hw/nios2/10m50_devboard.c13
1 files changed, 2 insertions, 11 deletions
diff --git a/hw/nios2/10m50_devboard.c b/hw/nios2/10m50_devboard.c
index 5c13b74306..a14fc31e86 100644
--- a/hw/nios2/10m50_devboard.c
+++ b/hw/nios2/10m50_devboard.c
@@ -52,7 +52,7 @@ static void nios2_10m50_ghrd_init(MachineState *machine)
ram_addr_t tcm_size = 0x1000; /* 1 kiB, but QEMU limit is 4 kiB */
ram_addr_t ram_base = 0x08000000;
ram_addr_t ram_size = 0x08000000;
- qemu_irq *cpu_irq, irq[32];
+ qemu_irq irq[32];
int i;
/* Physical TCM (tb_ram_1k) with alias at 0xc0000000 */
@@ -75,17 +75,8 @@ static void nios2_10m50_ghrd_init(MachineState *machine)
/* Create CPU -- FIXME */
cpu = NIOS2_CPU(cpu_create(TYPE_NIOS2_CPU));
-
- /* Register: CPU interrupt controller (PIC) */
- cpu_irq = nios2_cpu_pic_init(cpu);
-
- /* Register: Internal Interrupt Controller (IIC) */
- dev = qdev_new("altera,iic");
- object_property_add_const_link(OBJECT(dev), "cpu", OBJECT(cpu));
- sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
- sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq[0]);
for (i = 0; i < 32; i++) {
- irq[i] = qdev_get_gpio_in(dev, i);
+ irq[i] = qdev_get_gpio_in_named(DEVICE(cpu), "IRQ", i);
}
/* Register: Altera 16550 UART */