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authorPeter Maydell <peter.maydell@linaro.org>2020-09-03 14:12:48 +0100
committerPeter Maydell <peter.maydell@linaro.org>2020-09-03 14:12:48 +0100
commit3dd23a4fb8fd72d2220a90a809f213999ffe7f3a (patch)
treee45f68da4c497881301b8b773817810f0acdde02 /hw/net
parente4d8b7c1a95fffcfa4bdab9aa7ffd1cf590cdcf5 (diff)
parentddd8ab19749b8639fc08bfe4d0df0204eec049f0 (diff)
Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20200901' into staging
Various fixes of Aspeed machines : * New Supermicro X11 BMC machine (Erik) * Fixed valid access size on AST2400 SCU * Improved robustness of the ftgmac100 model. * New flash models in m25p80 (Igor) * Fixed reset sequence of SDHCI/eMMC controllers * Improved support of the AST2600 SDMC (Joel) * Couple of SMC cleanups # gpg: Signature made Tue 01 Sep 2020 13:39:20 BST # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * remotes/legoater/tags/pull-aspeed-20200901: hw: add a number of SPI-flash's of m25p80 family arm: aspeed: add strap define `25HZ` of AST2500 aspeed/smc: Open AHB window of the second chip of the AST2600 FMC controller aspeed/sdmc: Simplify calculation of RAM bits aspeed/sdmc: Allow writes to unprotected registers aspeed/sdmc: Perform memory training ftgmac100: Improve software reset ftgmac100: Fix integer overflow in ftgmac100_do_tx() ftgmac100: Check for invalid len and address before doing a DMA transfer ftgmac100: Change interrupt status when a DMA error occurs ftgmac100: Fix interrupt status "Packet moved to RX FIFO" ftgmac100: Fix interrupt status "Packet transmitted on ethernet" ftgmac100: Fix registers that can be read aspeed/sdhci: Fix reset sequence aspeed/smc: Fix max_slaves of the legacy SMC device aspeed/smc: Fix MemoryRegionOps definition hw/arm/aspeed: Add board model for Supermicro X11 BMC aspeed/scu: Fix valid access size on AST2400 m25p80: Add support for n25q512ax3 m25p80: Return the JEDEC ID twice for mx25l25635e Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/net')
-rw-r--r--hw/net/ftgmac100.c95
1 files changed, 68 insertions, 27 deletions
diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c
index 5f4b26fc5f..782ff192ce 100644
--- a/hw/net/ftgmac100.c
+++ b/hw/net/ftgmac100.c
@@ -481,6 +481,37 @@ static int ftgmac100_write_bd(FTGMAC100Desc *bd, dma_addr_t addr)
return 0;
}
+static int ftgmac100_insert_vlan(FTGMAC100State *s, int frame_size,
+ uint8_t vlan_tci)
+{
+ uint8_t *vlan_hdr = s->frame + (ETH_ALEN * 2);
+ uint8_t *payload = vlan_hdr + sizeof(struct vlan_header);
+
+ if (frame_size < sizeof(struct eth_header)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: frame too small for VLAN insertion : %d bytes\n",
+ __func__, frame_size);
+ s->isr |= FTGMAC100_INT_XPKT_LOST;
+ goto out;
+ }
+
+ if (frame_size + sizeof(struct vlan_header) > sizeof(s->frame)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: frame too big : %d bytes\n",
+ __func__, frame_size);
+ s->isr |= FTGMAC100_INT_XPKT_LOST;
+ frame_size -= sizeof(struct vlan_header);
+ }
+
+ memmove(payload, vlan_hdr, frame_size - (ETH_ALEN * 2));
+ stw_be_p(vlan_hdr, ETH_P_VLAN);
+ stw_be_p(vlan_hdr + 2, vlan_tci);
+ frame_size += sizeof(struct vlan_header);
+
+out:
+ return frame_size;
+}
+
static void ftgmac100_do_tx(FTGMAC100State *s, uint32_t tx_ring,
uint32_t tx_descriptor)
{
@@ -507,6 +538,15 @@ static void ftgmac100_do_tx(FTGMAC100State *s, uint32_t tx_ring,
}
len = FTGMAC100_TXDES0_TXBUF_SIZE(bd.des0);
+ if (!len) {
+ /*
+ * 0 is an invalid size, however the HW does not raise any
+ * interrupt. Flag an error because the guest is buggy.
+ */
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid segment size\n",
+ __func__);
+ }
+
if (frame_size + len > sizeof(s->frame)) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: frame too big : %d bytes\n",
__func__, len);
@@ -517,29 +557,21 @@ static void ftgmac100_do_tx(FTGMAC100State *s, uint32_t tx_ring,
if (dma_memory_read(&address_space_memory, bd.des3, ptr, len)) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to read packet @ 0x%x\n",
__func__, bd.des3);
- s->isr |= FTGMAC100_INT_NO_NPTXBUF;
+ s->isr |= FTGMAC100_INT_AHB_ERR;
break;
}
- /* Check for VLAN */
- if (bd.des0 & FTGMAC100_TXDES0_FTS &&
- bd.des1 & FTGMAC100_TXDES1_INS_VLANTAG &&
- be16_to_cpu(PKT_GET_ETH_HDR(ptr)->h_proto) != ETH_P_VLAN) {
- if (frame_size + len + 4 > sizeof(s->frame)) {
- qemu_log_mask(LOG_GUEST_ERROR, "%s: frame too big : %d bytes\n",
- __func__, len);
- s->isr |= FTGMAC100_INT_XPKT_LOST;
- len = sizeof(s->frame) - frame_size - 4;
- }
- memmove(ptr + 16, ptr + 12, len - 12);
- stw_be_p(ptr + 12, ETH_P_VLAN);
- stw_be_p(ptr + 14, bd.des1);
- len += 4;
- }
-
ptr += len;
frame_size += len;
if (bd.des0 & FTGMAC100_TXDES0_LTS) {
+
+ /* Check for VLAN */
+ if (flags & FTGMAC100_TXDES1_INS_VLANTAG &&
+ be16_to_cpu(PKT_GET_ETH_HDR(s->frame)->h_proto) != ETH_P_VLAN) {
+ frame_size = ftgmac100_insert_vlan(s, frame_size,
+ FTGMAC100_TXDES1_VLANTAG_CI(flags));
+ }
+
if (flags & FTGMAC100_TXDES1_IP_CHKSUM) {
net_checksum_calculate(s->frame, frame_size);
}
@@ -547,9 +579,7 @@ static void ftgmac100_do_tx(FTGMAC100State *s, uint32_t tx_ring,
qemu_send_packet(qemu_get_queue(s->nic), s->frame, frame_size);
ptr = s->frame;
frame_size = 0;
- if (flags & FTGMAC100_TXDES1_TXIC) {
- s->isr |= FTGMAC100_INT_XPKT_ETH;
- }
+ s->isr |= FTGMAC100_INT_XPKT_ETH;
}
if (flags & FTGMAC100_TXDES1_TX2FIC) {
@@ -619,10 +649,8 @@ static uint32_t ftgmac100_rxpoll(FTGMAC100State *s)
return cnt / div[speed];
}
-static void ftgmac100_reset(DeviceState *d)
+static void ftgmac100_do_reset(FTGMAC100State *s, bool sw_reset)
{
- FTGMAC100State *s = FTGMAC100(d);
-
/* Reset the FTGMAC100 */
s->isr = 0;
s->ier = 0;
@@ -641,7 +669,12 @@ static void ftgmac100_reset(DeviceState *d)
s->fear1 = 0;
s->tpafcr = 0xf1;
- s->maccr = 0;
+ if (sw_reset) {
+ s->maccr &= FTGMAC100_MACCR_GIGA_MODE | FTGMAC100_MACCR_FAST_MODE;
+ } else {
+ s->maccr = 0;
+ }
+
s->phycr = 0;
s->phydata = 0;
s->fcr = 0x400;
@@ -650,6 +683,11 @@ static void ftgmac100_reset(DeviceState *d)
phy_reset(s);
}
+static void ftgmac100_reset(DeviceState *d)
+{
+ ftgmac100_do_reset(FTGMAC100(d), false);
+}
+
static uint64_t ftgmac100_read(void *opaque, hwaddr addr, unsigned size)
{
FTGMAC100State *s = FTGMAC100(opaque);
@@ -669,6 +707,10 @@ static uint64_t ftgmac100_read(void *opaque, hwaddr addr, unsigned size)
return s->math[0];
case FTGMAC100_MATH1:
return s->math[1];
+ case FTGMAC100_RXR_BADR:
+ return s->rx_ring;
+ case FTGMAC100_NPTXR_BADR:
+ return s->tx_ring;
case FTGMAC100_ITC:
return s->itc;
case FTGMAC100_DBLAC:
@@ -790,7 +832,7 @@ static void ftgmac100_write(void *opaque, hwaddr addr,
case FTGMAC100_MACCR: /* MAC Device control */
s->maccr = value;
if (value & FTGMAC100_MACCR_SW_RST) {
- ftgmac100_reset(DEVICE(s));
+ ftgmac100_do_reset(s, true);
}
if (ftgmac100_can_receive(qemu_get_queue(s->nic))) {
@@ -948,6 +990,7 @@ static ssize_t ftgmac100_receive(NetClientState *nc, const uint8_t *buf,
break;
}
+ s->isr |= FTGMAC100_INT_RPKT_FIFO;
addr = s->rx_descriptor;
while (size > 0) {
if (!ftgmac100_can_receive(nc)) {
@@ -999,8 +1042,6 @@ static ssize_t ftgmac100_receive(NetClientState *nc, const uint8_t *buf,
/* Last buffer in frame. */
bd.des0 |= flags | FTGMAC100_RXDES0_LRS;
s->isr |= FTGMAC100_INT_RPKT_BUF;
- } else {
- s->isr |= FTGMAC100_INT_RPKT_FIFO;
}
ftgmac100_write_bd(&bd, addr);
if (bd.des0 & s->rxdes0_edorr) {