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authorPhilippe Mathieu-Daudé <philmd@linaro.org>2023-01-10 22:29:47 +0100
committerThomas Huth <thuth@redhat.com>2023-01-18 11:14:34 +0100
commit883f2c591fee552067e160208b4fe0228dbabbb1 (patch)
tree3f3944303bb12228328e7ccace0791159295eef9 /hw/net
parent6e6761d8fb640cf3dc58735c050878847eb22fca (diff)
bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plx
The 'hwaddr' type is defined in "exec/hwaddr.h" as: hwaddr is the type of a physical address (its size can be different from 'target_ulong'). All definitions use the 'HWADDR_' prefix, except TARGET_FMT_plx: $ fgrep define include/exec/hwaddr.h #define HWADDR_H #define HWADDR_BITS 64 #define HWADDR_MAX UINT64_MAX #define TARGET_FMT_plx "%016" PRIx64 ^^^^^^ #define HWADDR_PRId PRId64 #define HWADDR_PRIi PRIi64 #define HWADDR_PRIo PRIo64 #define HWADDR_PRIu PRIu64 #define HWADDR_PRIx PRIx64 #define HWADDR_PRIX PRIX64 Since hwaddr's size can be *different* from target_ulong, it is very confusing to read one of its format using the 'TARGET_FMT_' prefix, normally used for the target_long / target_ulong types: $ fgrep TARGET_FMT_ include/exec/cpu-defs.h #define TARGET_FMT_lx "%08x" #define TARGET_FMT_ld "%d" #define TARGET_FMT_lu "%u" #define TARGET_FMT_lx "%016" PRIx64 #define TARGET_FMT_ld "%" PRId64 #define TARGET_FMT_lu "%" PRIu64 Apparently this format was missed during commit a8170e5e97 ("Rename target_phys_addr_t to hwaddr"), so complete it by doing a bulk-rename with: $ sed -i -e s/TARGET_FMT_plx/HWADDR_FMT_plx/g $(git grep -l TARGET_FMT_plx) Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230110212947.34557-1-philmd@linaro.org> [thuth: Fix some warnings from checkpatch.pl along the way] Signed-off-by: Thomas Huth <thuth@redhat.com>
Diffstat (limited to 'hw/net')
-rw-r--r--hw/net/allwinner-sun8i-emac.c4
-rw-r--r--hw/net/allwinner_emac.c4
-rw-r--r--hw/net/fsl_etsec/etsec.c4
-rw-r--r--hw/net/fsl_etsec/rings.c4
-rw-r--r--hw/net/pcnet.c4
-rw-r--r--hw/net/rocker/rocker.c26
-rw-r--r--hw/net/rocker/rocker_desc.c2
-rw-r--r--hw/net/xilinx_axienet.c4
-rw-r--r--hw/net/xilinx_ethlite.c6
9 files changed, 29 insertions, 29 deletions
diff --git a/hw/net/allwinner-sun8i-emac.c b/hw/net/allwinner-sun8i-emac.c
index ecc0245fe8..b861d8ff35 100644
--- a/hw/net/allwinner-sun8i-emac.c
+++ b/hw/net/allwinner-sun8i-emac.c
@@ -663,7 +663,7 @@ static uint64_t allwinner_sun8i_emac_read(void *opaque, hwaddr offset,
break;
default:
qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: read access to unknown "
- "EMAC register 0x" TARGET_FMT_plx "\n",
+ "EMAC register 0x" HWADDR_FMT_plx "\n",
offset);
}
@@ -760,7 +760,7 @@ static void allwinner_sun8i_emac_write(void *opaque, hwaddr offset,
break;
default:
qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: write access to unknown "
- "EMAC register 0x" TARGET_FMT_plx "\n",
+ "EMAC register 0x" HWADDR_FMT_plx "\n",
offset);
}
}
diff --git a/hw/net/allwinner_emac.c b/hw/net/allwinner_emac.c
index ddddf35c45..372e5b66da 100644
--- a/hw/net/allwinner_emac.c
+++ b/hw/net/allwinner_emac.c
@@ -304,7 +304,7 @@ static uint64_t aw_emac_read(void *opaque, hwaddr offset, unsigned size)
default:
qemu_log_mask(LOG_UNIMP,
"allwinner_emac: read access to unknown register 0x"
- TARGET_FMT_plx "\n", offset);
+ HWADDR_FMT_plx "\n", offset);
ret = 0;
}
@@ -407,7 +407,7 @@ static void aw_emac_write(void *opaque, hwaddr offset, uint64_t value,
default:
qemu_log_mask(LOG_UNIMP,
"allwinner_emac: write access to unknown register 0x"
- TARGET_FMT_plx "\n", offset);
+ HWADDR_FMT_plx "\n", offset);
}
}
diff --git a/hw/net/fsl_etsec/etsec.c b/hw/net/fsl_etsec/etsec.c
index b75d8e3dce..c753bfb3a8 100644
--- a/hw/net/fsl_etsec/etsec.c
+++ b/hw/net/fsl_etsec/etsec.c
@@ -99,7 +99,7 @@ static uint64_t etsec_read(void *opaque, hwaddr addr, unsigned size)
break;
}
- DPRINTF("Read 0x%08x @ 0x" TARGET_FMT_plx
+ DPRINTF("Read 0x%08x @ 0x" HWADDR_FMT_plx
" : %s (%s)\n",
ret, addr, reg->name, reg->desc);
@@ -276,7 +276,7 @@ static void etsec_write(void *opaque,
}
}
- DPRINTF("Write 0x%08x @ 0x" TARGET_FMT_plx
+ DPRINTF("Write 0x%08x @ 0x" HWADDR_FMT_plx
" val:0x%08x->0x%08x : %s (%s)\n",
(unsigned int)value, addr, before, reg->value,
reg->name, reg->desc);
diff --git a/hw/net/fsl_etsec/rings.c b/hw/net/fsl_etsec/rings.c
index a32589e33b..788463f1b6 100644
--- a/hw/net/fsl_etsec/rings.c
+++ b/hw/net/fsl_etsec/rings.c
@@ -109,7 +109,7 @@ static void read_buffer_descriptor(eTSEC *etsec,
{
assert(bd != NULL);
- RING_DEBUG("READ Buffer Descriptor @ 0x" TARGET_FMT_plx"\n", addr);
+ RING_DEBUG("READ Buffer Descriptor @ 0x" HWADDR_FMT_plx"\n", addr);
cpu_physical_memory_read(addr,
bd,
sizeof(eTSEC_rxtx_bd));
@@ -141,7 +141,7 @@ static void write_buffer_descriptor(eTSEC *etsec,
stl_be_p(&bd->bufptr, bd->bufptr);
}
- RING_DEBUG("Write Buffer Descriptor @ 0x" TARGET_FMT_plx"\n", addr);
+ RING_DEBUG("Write Buffer Descriptor @ 0x" HWADDR_FMT_plx"\n", addr);
cpu_physical_memory_write(addr,
bd,
sizeof(eTSEC_rxtx_bd));
diff --git a/hw/net/pcnet.c b/hw/net/pcnet.c
index e63e524913..d456094575 100644
--- a/hw/net/pcnet.c
+++ b/hw/net/pcnet.c
@@ -908,11 +908,11 @@ static void pcnet_rdte_poll(PCNetState *s)
s->csr[37] = nnrd >> 16;
#ifdef PCNET_DEBUG
if (bad) {
- printf("pcnet: BAD RMD RECORDS AFTER 0x" TARGET_FMT_plx "\n",
+ printf("pcnet: BAD RMD RECORDS AFTER 0x" HWADDR_FMT_plx "\n",
crda);
}
} else {
- printf("pcnet: BAD RMD RDA=0x" TARGET_FMT_plx "\n", crda);
+ printf("pcnet: BAD RMD RDA=0x" HWADDR_FMT_plx "\n", crda);
#endif
}
}
diff --git a/hw/net/rocker/rocker.c b/hw/net/rocker/rocker.c
index cf54ddf49d..7ea8eb6ba5 100644
--- a/hw/net/rocker/rocker.c
+++ b/hw/net/rocker/rocker.c
@@ -815,7 +815,7 @@ static void rocker_io_writel(void *opaque, hwaddr addr, uint32_t val)
}
break;
default:
- DPRINTF("not implemented dma reg write(l) addr=0x" TARGET_FMT_plx
+ DPRINTF("not implemented dma reg write(l) addr=0x" HWADDR_FMT_plx
" val=0x%08x (ring %d, addr=0x%02x)\n",
addr, val, index, offset);
break;
@@ -857,7 +857,7 @@ static void rocker_io_writel(void *opaque, hwaddr addr, uint32_t val)
r->lower32 = 0;
break;
default:
- DPRINTF("not implemented write(l) addr=0x" TARGET_FMT_plx
+ DPRINTF("not implemented write(l) addr=0x" HWADDR_FMT_plx
" val=0x%08x\n", addr, val);
break;
}
@@ -876,8 +876,8 @@ static void rocker_io_writeq(void *opaque, hwaddr addr, uint64_t val)
desc_ring_set_base_addr(r->rings[index], val);
break;
default:
- DPRINTF("not implemented dma reg write(q) addr=0x" TARGET_FMT_plx
- " val=0x" TARGET_FMT_plx " (ring %d, offset=0x%02x)\n",
+ DPRINTF("not implemented dma reg write(q) addr=0x" HWADDR_FMT_plx
+ " val=0x" HWADDR_FMT_plx " (ring %d, offset=0x%02x)\n",
addr, val, index, offset);
break;
}
@@ -895,8 +895,8 @@ static void rocker_io_writeq(void *opaque, hwaddr addr, uint64_t val)
rocker_port_phys_enable_write(r, val);
break;
default:
- DPRINTF("not implemented write(q) addr=0x" TARGET_FMT_plx
- " val=0x" TARGET_FMT_plx "\n", addr, val);
+ DPRINTF("not implemented write(q) addr=0x" HWADDR_FMT_plx
+ " val=0x" HWADDR_FMT_plx "\n", addr, val);
break;
}
}
@@ -987,8 +987,8 @@ static const char *rocker_reg_name(void *opaque, hwaddr addr)
static void rocker_mmio_write(void *opaque, hwaddr addr, uint64_t val,
unsigned size)
{
- DPRINTF("Write %s addr " TARGET_FMT_plx
- ", size %u, val " TARGET_FMT_plx "\n",
+ DPRINTF("Write %s addr " HWADDR_FMT_plx
+ ", size %u, val " HWADDR_FMT_plx "\n",
rocker_reg_name(opaque, addr), addr, size, val);
switch (size) {
@@ -1060,7 +1060,7 @@ static uint32_t rocker_io_readl(void *opaque, hwaddr addr)
ret = desc_ring_get_credits(r->rings[index]);
break;
default:
- DPRINTF("not implemented dma reg read(l) addr=0x" TARGET_FMT_plx
+ DPRINTF("not implemented dma reg read(l) addr=0x" HWADDR_FMT_plx
" (ring %d, addr=0x%02x)\n", addr, index, offset);
ret = 0;
break;
@@ -1115,7 +1115,7 @@ static uint32_t rocker_io_readl(void *opaque, hwaddr addr)
ret = (uint32_t)(r->switch_id >> 32);
break;
default:
- DPRINTF("not implemented read(l) addr=0x" TARGET_FMT_plx "\n", addr);
+ DPRINTF("not implemented read(l) addr=0x" HWADDR_FMT_plx "\n", addr);
ret = 0;
break;
}
@@ -1136,7 +1136,7 @@ static uint64_t rocker_io_readq(void *opaque, hwaddr addr)
ret = desc_ring_get_base_addr(r->rings[index]);
break;
default:
- DPRINTF("not implemented dma reg read(q) addr=0x" TARGET_FMT_plx
+ DPRINTF("not implemented dma reg read(q) addr=0x" HWADDR_FMT_plx
" (ring %d, addr=0x%02x)\n", addr, index, offset);
ret = 0;
break;
@@ -1165,7 +1165,7 @@ static uint64_t rocker_io_readq(void *opaque, hwaddr addr)
ret = r->switch_id;
break;
default:
- DPRINTF("not implemented read(q) addr=0x" TARGET_FMT_plx "\n", addr);
+ DPRINTF("not implemented read(q) addr=0x" HWADDR_FMT_plx "\n", addr);
ret = 0;
break;
}
@@ -1174,7 +1174,7 @@ static uint64_t rocker_io_readq(void *opaque, hwaddr addr)
static uint64_t rocker_mmio_read(void *opaque, hwaddr addr, unsigned size)
{
- DPRINTF("Read %s addr " TARGET_FMT_plx ", size %u\n",
+ DPRINTF("Read %s addr " HWADDR_FMT_plx ", size %u\n",
rocker_reg_name(opaque, addr), addr, size);
switch (size) {
diff --git a/hw/net/rocker/rocker_desc.c b/hw/net/rocker/rocker_desc.c
index f3068c9250..675383db36 100644
--- a/hw/net/rocker/rocker_desc.c
+++ b/hw/net/rocker/rocker_desc.c
@@ -104,7 +104,7 @@ static bool desc_ring_empty(DescRing *ring)
bool desc_ring_set_base_addr(DescRing *ring, uint64_t base_addr)
{
if (base_addr & 0x7) {
- DPRINTF("ERROR: ring[%d] desc base addr (0x" TARGET_FMT_plx
+ DPRINTF("ERROR: ring[%d] desc base addr (0x" HWADDR_FMT_plx
") not 8-byte aligned\n", ring->index, base_addr);
return false;
}
diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c
index 990ff3a1c2..7e00965323 100644
--- a/hw/net/xilinx_axienet.c
+++ b/hw/net/xilinx_axienet.c
@@ -524,7 +524,7 @@ static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size)
if (addr < ARRAY_SIZE(s->regs)) {
r = s->regs[addr];
}
- DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n",
+ DENET(qemu_log("%s addr=" HWADDR_FMT_plx " v=%x\n",
__func__, addr * 4, r));
break;
}
@@ -630,7 +630,7 @@ static void enet_write(void *opaque, hwaddr addr,
break;
default:
- DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n",
+ DENET(qemu_log("%s addr=" HWADDR_FMT_plx " v=%x\n",
__func__, addr * 4, (unsigned)value));
if (addr < ARRAY_SIZE(s->regs)) {
s->regs[addr] = value;
diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c
index 6e09f7e422..99c22819ea 100644
--- a/hw/net/xilinx_ethlite.c
+++ b/hw/net/xilinx_ethlite.c
@@ -99,7 +99,7 @@ eth_read(void *opaque, hwaddr addr, unsigned int size)
case R_RX_CTRL1:
case R_RX_CTRL0:
r = s->regs[addr];
- D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr * 4, r));
+ D(qemu_log("%s " HWADDR_FMT_plx "=%x\n", __func__, addr * 4, r));
break;
default:
@@ -125,7 +125,7 @@ eth_write(void *opaque, hwaddr addr,
if (addr == R_TX_CTRL1)
base = 0x800 / 4;
- D(qemu_log("%s addr=" TARGET_FMT_plx " val=%x\n",
+ D(qemu_log("%s addr=" HWADDR_FMT_plx " val=%x\n",
__func__, addr * 4, value));
if ((value & (CTRL_P | CTRL_S)) == CTRL_S) {
qemu_send_packet(qemu_get_queue(s->nic),
@@ -155,7 +155,7 @@ eth_write(void *opaque, hwaddr addr,
case R_TX_LEN0:
case R_TX_LEN1:
case R_TX_GIE0:
- D(qemu_log("%s addr=" TARGET_FMT_plx " val=%x\n",
+ D(qemu_log("%s addr=" HWADDR_FMT_plx " val=%x\n",
__func__, addr * 4, value));
s->regs[addr] = value;
break;