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authorPeter Maydell <peter.maydell@linaro.org>2018-05-04 18:05:50 +0100
committerPeter Maydell <peter.maydell@linaro.org>2018-05-04 18:05:50 +0100
commit50a22d0de84955692a5f31134d88c1e8fea80247 (patch)
treed07398ad4d203fa0f62d840fd49125a888ce5f5d /hw/net/smc91c111.c
parenta22cadbefd2b2ff57f5c06688f7ed06c52d6929a (diff)
hw/net/smc91c111: Convert away from old_mmio
Convert the smc91c111 device away from using the old_mmio field of MemoryRegionOps. This device is used by several Arm board models. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180427173611.10281-3-peter.maydell@linaro.org
Diffstat (limited to 'hw/net/smc91c111.c')
-rw-r--r--hw/net/smc91c111.c54
1 files changed, 25 insertions, 29 deletions
diff --git a/hw/net/smc91c111.c b/hw/net/smc91c111.c
index 3b16dcf5a1..c8cc5379b7 100644
--- a/hw/net/smc91c111.c
+++ b/hw/net/smc91c111.c
@@ -625,37 +625,33 @@ static uint32_t smc91c111_readb(void *opaque, hwaddr offset)
return 0;
}
-static void smc91c111_writew(void *opaque, hwaddr offset,
- uint32_t value)
-{
- smc91c111_writeb(opaque, offset, value & 0xff);
- smc91c111_writeb(opaque, offset + 1, value >> 8);
-}
-
-static void smc91c111_writel(void *opaque, hwaddr offset,
- uint32_t value)
+static uint64_t smc91c111_readfn(void *opaque, hwaddr addr, unsigned size)
{
- /* 32-bit writes to offset 0xc only actually write to the bank select
- register (offset 0xe) */
- if (offset != 0xc)
- smc91c111_writew(opaque, offset, value & 0xffff);
- smc91c111_writew(opaque, offset + 2, value >> 16);
-}
+ int i;
+ uint32_t val = 0;
-static uint32_t smc91c111_readw(void *opaque, hwaddr offset)
-{
- uint32_t val;
- val = smc91c111_readb(opaque, offset);
- val |= smc91c111_readb(opaque, offset + 1) << 8;
+ for (i = 0; i < size; i++) {
+ val |= smc91c111_readb(opaque, addr + i) << (i * 8);
+ }
return val;
}
-static uint32_t smc91c111_readl(void *opaque, hwaddr offset)
+static void smc91c111_writefn(void *opaque, hwaddr addr,
+ uint64_t value, unsigned size)
{
- uint32_t val;
- val = smc91c111_readw(opaque, offset);
- val |= smc91c111_readw(opaque, offset + 2) << 16;
- return val;
+ int i = 0;
+
+ /* 32-bit writes to offset 0xc only actually write to the bank select
+ * register (offset 0xe), so skip the first two bytes we would write.
+ */
+ if (addr == 0xc && size == 4) {
+ i += 2;
+ }
+
+ for (; i < size; i++) {
+ smc91c111_writeb(opaque, addr + i,
+ extract32(value, i * 8, 8));
+ }
}
static int smc91c111_can_receive_nc(NetClientState *nc)
@@ -747,10 +743,10 @@ static const MemoryRegionOps smc91c111_mem_ops = {
/* The special case for 32 bit writes to 0xc means we can't just
* set .impl.min/max_access_size to 1, unfortunately
*/
- .old_mmio = {
- .read = { smc91c111_readb, smc91c111_readw, smc91c111_readl, },
- .write = { smc91c111_writeb, smc91c111_writew, smc91c111_writel, },
- },
+ .read = smc91c111_readfn,
+ .write = smc91c111_writefn,
+ .valid.min_access_size = 1,
+ .valid.max_access_size = 4,
.endianness = DEVICE_NATIVE_ENDIAN,
};