diff options
| author | Leonid Bloch <leonid.bloch@ravellosystems.com> | 2015-11-11 15:52:39 +0200 |
|---|---|---|
| committer | Jason Wang <jasowang@redhat.com> | 2015-11-12 13:48:53 +0800 |
| commit | 20f3e86362758b5085aa17baa7bc109c858acf67 (patch) | |
| tree | 46f36012d38893cc58e284c8c120e2b2d178e437 /hw/net/e1000_regs.h | |
| parent | ecc804cac31cec6cb90feaa459503afda8b38d09 (diff) | |
e1000: Cosmetic and alignment fixes
This fixes some alignment and cosmetic issues. The changes are made
in order that the following patches in this series will look like
integral parts of the code surrounding them, while conforming to the
coding style. Although some changes in unrelated areas are also made.
Signed-off-by: Leonid Bloch <leonid.bloch@ravellosystems.com>
Signed-off-by: Dmitry Fleytman <dmitry.fleytman@ravellosystems.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Diffstat (limited to 'hw/net/e1000_regs.h')
| -rw-r--r-- | hw/net/e1000_regs.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/net/e1000_regs.h b/hw/net/e1000_regs.h index 60b96aaf13..afd81cc965 100644 --- a/hw/net/e1000_regs.h +++ b/hw/net/e1000_regs.h @@ -158,7 +158,7 @@ #define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */ #define FEXTNVM_SW_CONFIG 0x0001 #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ -#define E1000_PBS 0x01008 /* Packet Buffer Size */ +#define E1000_PBS 0x01008 /* Packet Buffer Size - RW */ #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ #define E1000_FLASH_UPDATES 1000 #define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */ |