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authorSebastian Huber <sebastian.huber@embedded-brains.de>2014-02-05 08:31:55 +0100
committerPeter Maydell <peter.maydell@linaro.org>2014-02-08 14:50:48 +0000
commit69991d7dcbcf7f3fe38274bc67fcba3cbbfda0cf (patch)
tree097276492e0349e104ab56269ddb29a80ce2c513 /hw/misc
parentdb7dfd4c7e4450b10048a53ce67bcac6305ad383 (diff)
arm/zynq: Add software system reset via SCLR
Support software-driven system reset via the register in the SCLR. Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/misc')
-rw-r--r--hw/misc/zynq_slcr.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c
index e42a5b04ab..d1cc23303a 100644
--- a/hw/misc/zynq_slcr.c
+++ b/hw/misc/zynq_slcr.c
@@ -31,6 +31,8 @@
#define XILINX_LOCK_KEY 0x767b
#define XILINX_UNLOCK_KEY 0xdf0d
+#define R_PSS_RST_CTRL_SOFT_RST 0x1
+
typedef enum {
ARM_PLL_CTRL,
DDR_PLL_CTRL,
@@ -399,6 +401,9 @@ static void zynq_slcr_write(void *opaque, hwaddr offset,
goto bad_reg;
}
s->reset[(offset - 0x200) / 4] = val;
+ if (offset == 0x200 && (val & R_PSS_RST_CTRL_SOFT_RST)) {
+ qemu_system_reset_request();
+ }
break;
case 0x300:
s->apu_ctrl = val;