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authorPeter Maydell <peter.maydell@linaro.org>2022-08-02 14:19:25 +0100
committerPhilippe Mathieu-Daudé <f4bug@amsat.org>2022-08-08 23:43:11 +0200
commit09d12c81ec5d8dc9208e5739d17a56c34be96247 (patch)
treed40a96be4fe7863778f654666e3aae2bd5c979f1 /hw/misc/trace-events
parentbd64c210ce2bebba993ee49d34327706ec47f685 (diff)
hw/misc/grlib_ahb_apb_pnp: Support 8 and 16 bit accesses
In real hardware, the APB and AHB PNP data tables can be accessed with byte and halfword reads as well as word reads. Our implementation currently only handles word reads. Add support for the 8 and 16 bit accesses. Note that we only need to handle aligned accesses -- unaligned accesses should continue to trap, as happens on hardware. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1132 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Frederic Konrad <fkonrad@amd.com> Message-Id: <20220802131925.3380923-1-peter.maydell@linaro.org> Tested-by: Tomasz Martyniak <gitlab.com/tom4r> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'hw/misc/trace-events')
-rw-r--r--hw/misc/trace-events4
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index 4d51a80de1..c18bc0605e 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -247,8 +247,8 @@ via1_adb_poll(uint8_t data, const char *vadbint, int status, int index, int size
via1_auxmode(int mode) "setting auxmode to %d"
# grlib_ahb_apb_pnp.c
-grlib_ahb_pnp_read(uint64_t addr, uint32_t value) "AHB PnP read addr:0x%03"PRIx64" data:0x%08x"
-grlib_apb_pnp_read(uint64_t addr, uint32_t value) "APB PnP read addr:0x%03"PRIx64" data:0x%08x"
+grlib_ahb_pnp_read(uint64_t addr, unsigned size, uint32_t value) "AHB PnP read addr:0x%03"PRIx64" size:%u data:0x%08x"
+grlib_apb_pnp_read(uint64_t addr, unsigned size, uint32_t value) "APB PnP read addr:0x%03"PRIx64" size:%u data:0x%08x"
# led.c
led_set_intensity(const char *color, const char *desc, uint8_t intensity_percent) "LED desc:'%s' color:%s intensity: %u%%"