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| author | Peter Maydell <peter.maydell@linaro.org> | 2017-07-31 14:45:42 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-07-31 14:45:42 +0100 |
| commit | 5619c179057e24195ff19c8fe6d6a6cbcb16ed28 (patch) | |
| tree | 5d2f1166996202e5d26cc5a59098ec8ef0634b7f /hw/misc/mps2-scc.c | |
| parent | bdf211f884113426e1f8226b69731593efa003ea (diff) | |
| parent | 89cbc3778a3d61761e2231e740269218c9a8a41d (diff) | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170731' into staging
target-arm queue:
* fix broken properties on MPS2 SCC device
* fix MPU trace handling of write vs exec
* fix MPU M profile bugs:
- not handling system space or PPB region correctly
- not resetting state
- not migrating MPU_RNR
# gpg: Signature made Mon 31 Jul 2017 13:21:40 BST
# gpg: using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg: aka "Peter Maydell <pmaydell@gmail.com>"
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20170731:
hw/mps2_scc: fix incorrect properties
target/arm: Migrate MPU_RNR register state for M profile cores
target/arm: Move PMSAv7 reset into arm_cpu_reset() so M profile MPUs get reset
target/arm: Rename cp15.c6_rgnr to pmsav7.rnr
target/arm: Don't allow guest to make System space executable for M profile
target/arm: Don't do MPU lookups for addresses in M profile PPB region
target/arm: Correct MPU trace handling of write vs execute
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/misc/mps2-scc.c')
| -rw-r--r-- | hw/misc/mps2-scc.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c index cc58d26f29..32be2a9df1 100644 --- a/hw/misc/mps2-scc.c +++ b/hw/misc/mps2-scc.c @@ -270,9 +270,9 @@ static Property mps2_scc_properties[] = { /* Values for various read-only ID registers (which are specific * to the board model or FPGA image) */ - DEFINE_PROP_UINT32("scc-cfg4", MPS2SCC, aid, 0), + DEFINE_PROP_UINT32("scc-cfg4", MPS2SCC, cfg4, 0), DEFINE_PROP_UINT32("scc-aid", MPS2SCC, aid, 0), - DEFINE_PROP_UINT32("scc-id", MPS2SCC, aid, 0), + DEFINE_PROP_UINT32("scc-id", MPS2SCC, id, 0), /* These are the initial settings for the source clocks on the board. * In hardware they can be configured via a config file read by the * motherboard configuration controller to suit the FPGA image. |