diff options
| author | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 2021-03-08 23:46:36 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-03-12 12:40:09 +0000 |
| commit | 9f61763574fb19525a68c46f3b8f763e5936a6fe (patch) | |
| tree | 0465fcd543f6de9b77c45baf86cdb4184ee287be /hw/misc/meson.build | |
| parent | 6f34661b6c97a37a5efc27d31c037ddeda4547e2 (diff) | |
hw/misc: versal: Add a model of the XRAM controller
Add a model of the Xilinx Versal Accelerator RAM (XRAM).
This is mainly a stub to make firmware happy. The size of
the RAMs can be probed. The interrupt mask logic is
modelled but none of the interrups will ever be raised
unless injected.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20210308224637.2949533-2-edgar.iglesias@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/misc/meson.build')
| -rw-r--r-- | hw/misc/meson.build | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 00356cf12e..65b6bb06b0 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -85,6 +85,7 @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files( )) softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c')) softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c', 'zynq-xadc.c')) +softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-xramc.c')) softmmu_ss.add(when: 'CONFIG_STM32F2XX_SYSCFG', if_true: files('stm32f2xx_syscfg.c')) softmmu_ss.add(when: 'CONFIG_STM32F4XX_SYSCFG', if_true: files('stm32f4xx_syscfg.c')) softmmu_ss.add(when: 'CONFIG_STM32F4XX_EXTI', if_true: files('stm32f4xx_exti.c')) |